LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 696

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
11. JTAG Flash programming interface
UM10237_4
User manual
10.9 IAP Status Codes
Table 628. Reinvoke ISP
Table 629. IAP Status Codes Summary
Debug tools can write parts of the Flash image to the RAM and then execute the IAP call
"Copy RAM to Flash" repeatedly with proper offset.
Command
Return Code
Result
Description
Status
Code
0
1
2
3
4
5
6
7
8
9
10
11
Mnemonic
CMD_SUCCESS
INVALID_COMMAND
SRC_ADDR_ERROR
DST_ADDR_ERROR
SRC_ADDR_NOT_MAPPED
DST_ADDR_NOT_MAPPED
COUNT_ERROR
INVALID_SECTOR
SECTOR_NOT_BLANK
SECTOR_NOT_PREPARED_
FOR_WRITE_OPERATION
COMPARE_ERROR
BUSY
Compare
None
None.
This command is used to invoke the bootloader in ISP mode. It maps boot
vectors, sets PCLK = CCLK / 4, configures UART0 pins Rx and Tx, resets
TIMER1 and resets the U0FDR (see
used when a valid user program is present in the internal Flash memory and the
P2.10 pin is not accessible to force the ISP mode. The command does not disable
the PLL hence it is possible to invoke the bootloader when the part is running off
the PLL. In such case the ISP utility should pass the CCLK (crystal or PLL output
depending on the clock source selection
autobaud handshake.
Another option is to disable the PLL and select the IRC as the clock source before
making this IAP call. In this case frequency sent by ISP is ignored and IRC and
PLL are used to generate CCLK = 14.748 MHz.
Rev. 04 — 26 August 2009
Chapter 30: LPC24XX Flash memory programming firmware
Description
Command is executed successfully.
Invalid command.
Source address is not on a word boundary.
Destination address is not on a correct boundary.
Source address is not mapped in the memory map.
Count value is taken in to consideration where
applicable.
Destination address is not mapped in the memory
map. Count value is taken in to consideration where
applicable.
Byte count is not multiple of 4 or is not a permitted
value.
Sector number is invalid.
Sector is not blank.
Command to prepare sector for write operation was
not executed.
Source and destination data is not same.
Flash programming hardware interface is busy.
Section
Section
16–4.12). This command may be
4–3.1.1) frequency after
UM10237
© NXP B.V. 2009. All rights reserved.
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