LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 534
LPC2458FET180,551
Manufacturer Part Number
LPC2458FET180,551
Description
IC ARM7 MCU FLASH 512K 180TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2458FET180,551
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
136
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
180-TFBGA
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
32 bit
Data Ram Size
98 KB
Interface Type
CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
136
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 1 Channel
Package
180TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
For Use With
622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4258
935282454551
LPC2458FET180-S
935282454551
LPC2458FET180-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2458FET180,551
Manufacturer:
MICROCHIP
Quantity:
1 103
Company:
Part Number:
LPC2458FET180,551
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NXP Semiconductors
Quantity:
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8. Architecture
UM10237_4
User manual
7.6 SPI Test Status Register (SPTSR - 0xE002 0014)
7.7 SPI Interrupt Register (S0SPINT - 0xE002 001C)
Table 466: SPI Test Control Register (SPTCR - address 0xE002 0010) bit description
Note: The bits in this register are intended for functional verification only. This register
should not be used for normal operation.
This register is a replication of the SPI status register. The difference between the
registers is that a read of this register will not start the sequence of events required to
clear these status bits. A write to this register will set an interrupt if the write data for the
respective bit is a 1.
Table 467: SPI Test Status Register (SPTSR - address 0xE002 0014) bit description
This register contains the interrupt flag for the SPI0 interface.
Table 468: SPI Interrupt Register (S0SPINT - address 0xE002 001C) bit description
The block diagram of the SPI solution implemented in SPI0 interface is shown in the
Figure
Bit
0
7:1
Bit
2:0
3
4
5
6
7
Bit Symbol Description
0
7:1 -
SPI
Interrupt
Flag
Symbol
-
Test
Symbol
-
ABRT
MODF
ROVR
WCOL
SPIF
19–95.
SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared
by writing a 1 to this bit.
Note: this bit will be set once when SPIE = 1 and at least one of SPIF and
WCOL bits is 1. However, only when the SPI Interrupt bit is set and SPI0
Interrupt is enabled in the VIC, SPI based interrupt can be processed by
interrupt handling software.
Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
Description
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
SPI test mode. When 0, the SPI operates normally. When 1,
SCK will always be on, independent of master mode select, and
data availability setting.
Description
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Slave abort.
Mode fault.
Read overrun.
Write collision.
SPI transfer complete flag.
Rev. 04 — 26 August 2009
Chapter 19: LPC24XX SPI
UM10237
© NXP B.V. 2009. All rights reserved.
0
Reset Value
NA
0
Reset Value
NA
0
0
0
0
534 of 792
Reset
Value
0
NA
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