LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 627

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
UM10237_4
User manual
6.8 Match Control Register (T[0/1/2/3]MCR - 0xE000 4014, 0xE000 8014,
0xE007 0014, 0xE007 4014)
The Match Control Register is used to control what operations are performed when one of
the Match Registers matches the Timer Counter. The function of each of the bits is shown
in
Table 550: Match Control Register (T[0/1/2/3]MCR - addresses 0xE000 4014, 0xE000 8014,
Bit
0
1
2
3
4
5
6
7
8
9
10
11
15:12 -
Table
Symbol Value Description
MR0I
MR0R
MR0S
MR1I
MR1R
MR1S
MR2I
MR2R
MR2S
MR3I
MR3R
MR3S
24–550.
0xE007 0014, 0xE007 4014) bit description
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Rev. 04 — 26 August 2009
Interrupt on MR0: an interrupt is generated when MR0 matches
the value in the TC.
This interrupt is disabled
Reset on MR0: the TC will be reset if MR0 matches it.
Feature disabled.
Stop on MR0: the TC and PC will be stopped and TCR[0] will be
set to 0 if MR0 matches the TC.
Feature disabled.
Interrupt on MR1: an interrupt is generated when MR1 matches
the value in the TC.
This interrupt is disabled
Reset on MR1: the TC will be reset if MR1 matches it.
Feature disabled.
Stop on MR1: the TC and PC will be stopped and TCR[0] will be
set to 0 if MR1 matches the TC.
Feature disabled.
Interrupt on MR2: an interrupt is generated when MR2 matches
the value in the TC.
This interrupt is disabled
Reset on MR2: the TC will be reset if MR2 matches it.
Feature disabled.
Stop on MR2: the TC and PC will be stopped and TCR[0] will be
set to 0 if MR2 matches the TC.
Feature disabled.
Interrupt on MR3: an interrupt is generated when MR3 matches
the value in the TC.
This interrupt is disabled
Reset on MR3: the TC will be reset if MR3 matches it.
Feature disabled.
Stop on MR3: the TC and PC will be stopped and TCR[0] will be
set to 0 if MR3 matches the TC.
Feature disabled.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Chapter 24: LPC24XX Timer0/1/2/3
UM10237
© NXP B.V. 2009. All rights reserved.
627 of 792
Reset
Value
0
0
0
0
0
0
0
0
0
0
0
0
NA