LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 641

IC ARM7 MCU FLASH 512K 180TFBGA

LPC2458FET180,551

Manufacturer Part Number
LPC2458FET180,551
Description
IC ARM7 MCU FLASH 512K 180TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets

Specifications of LPC2458FET180,551

Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
136
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
180-TFBGA
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
32 bit
Data Ram Size
98 KB
Interface Type
CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
136
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 1 Channel
Package
180TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
For Use With
622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
568-4258
935282454551
LPC2458FET180-S

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LPC2458FET180,551
Manufacturer:
MICROCHIP
Quantity:
1 103
Part Number:
LPC2458FET180,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
UM10237_4
User manual
6.3 PWM Count Control Register (PWM0CTCR - 0xE001 4070 and
6.4 PWM Match Control Register (PWM0MCR - 0xE001 4014 and
PWM1CTCR 0xE001 8070)
The Count Control Register (CTCR) is used to select between Timer and Counter mode,
and in Counter mode to select the pin and edge(s) for counting. The function of each of
the bits is shown in
Table 560: PWM Count control Register (PWM0TCR - address 0xE001 4004 and PWM1CTCR
[1]
PWM1MCR 0xE001 8014)
The PWM Match Control registers are used to control what operations are performed
when one of the PWM Match registers matches the PWM Timer Counter. The function of
each of the bits is shown in
Table 561: Match Control Register (PWM0MCR - address 0xE000 4014 and PWM1MCR -
Bit
1:0
3:2
7:4
Bit
0
1
2
PCAP input signal frequency must not exceed PCLK/4. When the PWM clock is supplied via the PCAP pin,
at no time high(low) level of the signal on this pin can last less than 1/(2
Symbol
PWMMR0I
PWMMR0R 1
PWMMR0S 1
Symbol
Counter/
Timer Mode
Count Input
Select
-
address 0xE001 8004) bit description
address 0xE000 8014) bit description
Value Description
1
0
0
0
Table
Rev. 04 — 26 August 2009
Description
00: Timer Mode: the TC is incremented when the
Prescale Counter matches the Prescale register.
01: Counter Mode: the TC is incremented on rising
edges of the PCAP input selected by bits 3:2.
10: Counter Mode: the TC is incremented on falling
edges of the PCAP input selected by bits 3:2.
11: Counter Mode: the TC is incremented on both edges
of the PCAP input selected by bits 3:2.
When bits 1:0 are not 00, these bits select which PCAP
pin carries the signal used to increment the TC.
For PWM0: 00 = PCAP0.0 (Other combinations are
reserved)
For PWM1: 00 = PCAP1.0, 01 = PCAP1.1(Other
combinations are reserved)
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
25–560.
Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1
Interrupt on PWMMR0: an interrupt is generated when
PWMMR0 matches the value in the PWMTC.
This interrupt is disabled.
Reset on PWMMR0: the PWMTC will be reset if PWMMR0
matches it.
This feature is disabled.
Stop on PWMMR0: the PWMTC and PWMPC will be stopped
and PWMTCR bt 0 will be set to 0 if PWMMR0 matches the
PWMTC.
This feature is disabled
Table
25–561.
×
PCLK).
UM10237
© NXP B.V. 2009. All rights reserved.
Reset Value
00
00
NA
641 of 792
Reset
Value
0
0
0

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