LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 409
LPC2458FET180,551
Manufacturer Part Number
LPC2458FET180,551
Description
IC ARM7 MCU FLASH 512K 180TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2458FET180,551
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
136
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
180-TFBGA
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
32 bit
Data Ram Size
98 KB
Interface Type
CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
136
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 1 Channel
Package
180TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
For Use With
622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4258
935282454551
LPC2458FET180-S
935282454551
LPC2458FET180-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2458FET180,551
Manufacturer:
MICROCHIP
Quantity:
1 103
Company:
Part Number:
LPC2458FET180,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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Table 373. I2C Control register (I2C_CTL - address 0xFFE0 C308) bit description
UM10237_4
User manual
Bit
3
4
5
6
7
8
31:9 -
Symbol
DRMIE
DRSIE
REFIE
RFDAIE
TFFIE
SRST
7.14 I2C Clock High Register (I2C_CLKHI - 0xFFE0 C30C)
Value Description
0
1
0
1
0
1
0
1
0
1
0
1
NA
The CLK register holds a terminal count for counting 48 MHz clock cycles to create the
high period of the slower I
Table 374. I2C_CLKHI register (I2C_CLKHI - address 0xFFE0 C30C) bit description
Master Transmitter Data Request Interrupt Enable. This enables the DRMI interrupt which
signals that the master transmitter has run out of data, has not issued a STOP, and is
holding the SCL line low.
Disable the DRMI interrupt.
Enable the DRMI interrupt.
Slave Transmitter Data Request Interrupt Enable. This enables the DRSI interrupt which
signals that the slave transmitter has run out of data and the last byte was acknowledged,
so the SCL line is being held low.
Disable the DRSI interrupt.
Enable the DRSI interrupt.
Receive FIFO Full Interrupt Enable. This enables the Receive FIFO Full interrupt to
indicate that the receive FIFO cannot accept any more data.
Disable the RFFI.
Enable the RFFI.
Receive Data Available Interrupt Enable. This enables the DAI interrupt to indicate that
data is available in the receive FIFO (i.e. not empty).
Disable the DAI.
Enable the DAI.
Transmit FIFO Not Full Interrupt Enable. This enables the Transmit FIFO Not Full interrupt
to indicate that the more data can be written to the transmit FIFO. Note that this is not full.
It is intended help the CPU to write to the I
and do this without polling the status register.
Disable the TFFI.
Enable the TFFI.
Soft reset. This is only needed in unusual circumstances. If a device issues a start
condition without issuing a stop condition. A system timer may be used to reset the I
the bus remains busy longer than the time-out period. On a soft reset, the Tx and Rx
FIFOs are flushed, I2C_STS register is cleared, and all internal state machines are reset
to appear idle. The I2C_CLKHI, I2C_CLKLO and I2C_CTL (except Soft Reset Bit) are
NOT modified by a soft reset.
See the text.
Reset the I
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Bit
7:0
Symbol
CDHI
2
C to idle state. Self clearing.
Rev. 04 — 26 August 2009
2
C serial clock, SCL.
Description
Clock divisor high. This value is the number of 48 MHz
clocks the serial clock (SCL) will be high.
2
C block only when there is room in the FIFO
Chapter 15: LPC24XX USB OTG controller
UM10237
© NXP B.V. 2009. All rights reserved.
2
C if
409 of 792
Reset
Value
0
0
0
0
0
0
NA
Reset
Value
0xB9
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