LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 102

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
4. Memory Acceleration Module blocks
UM10237_4
User manual
4.1 Flash memory bank
Branches and other program flow changes cause a break in the sequential flow of
instruction fetches described above. The Branch Trail buffer captures the line to which
such a non-sequential break occurs. If the same branch is taken again, the next
instruction is taken from the Branch Trail buffer. When a branch outside the contents of the
prefetch and Branch Trail buffer is taken, a stall of several clocks is needed to load the
Branch Trail buffer. Subsequently, there will typically be no further instruction fetch delays
until a new and different branch occurs.
If an attempt is made to write directly to the Flash memory, without using the normal Flash
programming interface, the MAM generates a data abort.
The Memory Accelerator Module is divided into several functional blocks:
Figure 6–20
paths.
In the following descriptions, the term “fetch” applies to an explicit Flash read request from
the ARM. “Pre-fetch” is used to denote a Flash read of instructions beyond the current
processor fetch address.
There is one bank of Flash memory for the LPC2400 MAM.
Flash programming operations are not controlled by the MAM, but are handled as a
separate function. A “boot block” sector contains Flash programming algorithms that may
be called as part of the application program, and a loader that may be run to allow serial
programming of the Flash memory.
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A Flash Address Latch and an incrementor function to form prefetch addresses
A 128 bit prefetch buffer and an associated Address latch and comparator
A 128 bit Branch Trail buffer and an associated Address latch and comparator
A 128 bit Data buffer and an associated Address latch and comparator
Control logic
Wait logic
shows a simplified block diagram of the Memory Accelerator Module data
Rev. 04 — 26 August 2009
Chapter 6: LPC24XX Memory Accelerator Module (MAM)
UM10237
© NXP B.V. 2009. All rights reserved.
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