LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 782

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
11
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
11.10
11.11
11.12
11.13
11.14
12
13
13.1
13.2
13.3
14
14.1
14.2
14.3
14.4
14.4.1
14.4.2
Chapter 14: LPC24XX USB Host controller
1
2
2.1
2.2
3
Chapter 15: LPC24XX USB OTG controller
1
2
UM10237_4
User manual
Serial interface engine command
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
USB device controller initialization . . . . . . . 372
Slave mode operation . . . . . . . . . . . . . . . . . . 373
DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 374
Basic configuration . . . . . . . . . . . . . . . . . . . . 389
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Basic configuration . . . . . . . . . . . . . . . . . . . . 394
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Slave mode. . . . . . . . . . . . . . . . . . . . . . . . . . .360
DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . .361
Set Address (Command: 0xD0, Data:
write 1 byte) . . . . . . . . . . . . . . . . . . . . . . . . . 364
Configure Device (Command: 0xD8, Data: write 1
byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Set Mode (Command: 0xF3, Data:
write 1 byte) . . . . . . . . . . . . . . . . . . . . . . . . . 365
Read Current Frame Number (Command: 0xF5,
Data: read 1 or 2 bytes) . . . . . . . . . . . . . . . . 366
Read Test Register (Command: 0xFD, Data: read
2 bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
Set Device Status (Command: 0xFE, Data: write 1
byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
Get Device Status (Command: 0xFE, Data: read 1
byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
Get Error Code (Command: 0xFF, Data: read 1
byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
Read Error Status (Command: 0xFB, Data: read 1
byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
Select Endpoint (Command: 0x00 - 0x1F, Data:
read 1 byte (optional)) . . . . . . . . . . . . . . . . . 369
Select Endpoint/Clear Interrupt (Command:
0x40 - 0x5F, Data: read 1 byte) . . . . . . . . . . 370
Set Endpoint Status (Command: 0x40 - 0x55,
Data: write 1 byte (optional)). . . . . . . . . . . . . 370
Clear Buffer (Command: 0xF2, Data: read 1 byte
(optional)) . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Validate Buffer (Command: 0xFA, Data:
none) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Interrupt generation . . . . . . . . . . . . . . . . . . . 373
Data transfer for OUT endpoints. . . . . . . . . . 373
Data transfer for IN endpoints. . . . . . . . . . . . 374
Transfer terminology. . . . . . . . . . . . . . . . . . . 374
USB device communication area . . . . . . . . . 375
Triggering the DMA engine. . . . . . . . . . . . . . 375
The DMA descriptor . . . . . . . . . . . . . . . . . . . 376
Next_DD_pointer . . . . . . . . . . . . . . . . . . . . . 377
DMA_mode. . . . . . . . . . . . . . . . . . . . . . . . . . 377
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 390
Rev. 04 — 26 August 2009
14.4.3
14.4.4
14.4.5
14.4.6
14.4.7
14.4.8
14.4.9
14.4.10
14.4.11
14.4.12
14.4.13
14.4.14
14.4.15
14.5
14.5.1
14.5.2
14.5.3
14.5.4
14.5.5
14.5.6
14.6
14.6.1
14.6.2
14.6.3
14.6.4
14.6.5
14.7
14.7.1
14.7.2
14.7.3
14.7.4
15
15.1
15.2
3.1
3.1.1
3.2
3.2.1
3.2.2
3
4
Chapter 36: LPC24XX Supplementary information
Double buffered endpoint operation . . . . . . 386
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Next_DD_valid . . . . . . . . . . . . . . . . . . . . . . . 377
Isochronous_endpoint . . . . . . . . . . . . . . . . . 377
Max_packet_size . . . . . . . . . . . . . . . . . . . . . 377
DMA_buffer_length . . . . . . . . . . . . . . . . . . . 378
DMA_buffer_start_addr . . . . . . . . . . . . . . . . 378
DD_retired . . . . . . . . . . . . . . . . . . . . . . . . . . 378
DD_status . . . . . . . . . . . . . . . . . . . . . . . . . . 378
Packet_valid. . . . . . . . . . . . . . . . . . . . . . . . . 378
LS_byte_extracted . . . . . . . . . . . . . . . . . . . . 379
MS_byte_extracted . . . . . . . . . . . . . . . . . . . 379
Present_DMA_count . . . . . . . . . . . . . . . . . . 379
Message_length_position . . . . . . . . . . . . . . 379
Isochronous_packetsize_memory_address. 379
Non-isochronous endpoint operation . . . . . . 379
Setting up DMA transfers. . . . . . . . . . . . . . . 379
Finding DMA Descriptor. . . . . . . . . . . . . . . . 379
Transferring the data . . . . . . . . . . . . . . . . . . 380
Optimizing descriptor fetch . . . . . . . . . . . . . 380
Ending the packet transfer . . . . . . . . . . . . . . 380
No_Packet DD . . . . . . . . . . . . . . . . . . . . . . . 381
Isochronous endpoint operation. . . . . . . . . . 381
Setting up DMA transfers. . . . . . . . . . . . . . . 381
Finding the DMA Descriptor. . . . . . . . . . . . . 381
Transferring the Data . . . . . . . . . . . . . . . . . . 381
OUT endpoints. . . . . . . . . . . . . . . . . . . . . . . . 382
IN endpoints. . . . . . . . . . . . . . . . . . . . . . . . . . 382
DMA descriptor completion . . . . . . . . . . . . . 382
Isochronous OUT Endpoint Operation
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
Auto Length Transfer Extraction (ATLE) mode
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
OUT transfers in ATLE mode. . . . . . . . . . . . . 383
IN transfers in ATLE mode. . . . . . . . . . . . . . . 385
Setting up the DMA transfer. . . . . . . . . . . . . 385
Finding the DMA Descriptor. . . . . . . . . . . . . 385
Transferring the Data . . . . . . . . . . . . . . . . . . 385
OUT endpoints. . . . . . . . . . . . . . . . . . . . . . . . 385
IN endpoints. . . . . . . . . . . . . . . . . . . . . . . . . . 385
Ending the packet transfer . . . . . . . . . . . . . . 386
OUT endpoints. . . . . . . . . . . . . . . . . . . . . . . . 386
IN endpoints. . . . . . . . . . . . . . . . . . . . . . . . . . 386
Bulk endpoints . . . . . . . . . . . . . . . . . . . . . . . 386
Isochronous endpoints . . . . . . . . . . . . . . . . . 388
Pin description . . . . . . . . . . . . . . . . . . . . . . . 390
USB host usage note . . . . . . . . . . . . . . . . . . 391
Software interface . . . . . . . . . . . . . . . . . . . . 391
Register map . . . . . . . . . . . . . . . . . . . . . . . . 391
USB Host Register Definitions . . . . . . . . . . . 393
UM10237
© NXP B.V. 2009. All rights reserved.
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