LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 539

IC ARM7 MCU FLASH 512K 180TFBGA

LPC2458FET180,551

Manufacturer Part Number
LPC2458FET180,551
Description
IC ARM7 MCU FLASH 512K 180TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets

Specifications of LPC2458FET180,551

Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
136
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
180-TFBGA
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
32 bit
Data Ram Size
98 KB
Interface Type
CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
136
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 1 Channel
Package
180TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
For Use With
622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
568-4258
935282454551
LPC2458FET180-S

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LPC2458FET180,551
Manufacturer:
MICROCHIP
Quantity:
1 103
Part Number:
LPC2458FET180,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
UM10237_4
User manual
Fig 97. SPI frame format with CPOL=0 and CPHA=0 (a) Single and b) Continuous Transfer)
a. Single transfer with CPOL=0 and CPHA=0
b. Continuous transfer with CPOL=0 and CPHA=0
SSEL
MOSI
MISO
SCK
5.2.2 SPI format with CPOL=0,CPHA=0
MSB
MSB
The CPHA control bit selects the clock edge that captures data and allows it to change
state. It has the most impact on the first bit transmitted by either allowing or not allowing a
clock transition before the first data capture edge. When the CPHA phase control bit is
LOW, data is captured on the first clock edge transition. If the CPHA clock phase control
bit is HIGH, data is captured on the second clock edge transition.
Single and continuous transmission signal sequences for SPI format with CPOL = 0,
CPHA = 0 are shown in
In this configuration, during idle periods:
If the SSP is enabled and there is valid data within the transmit FIFO, the start of
transmission is signified by the SSEL master signal being driven LOW. This causes slave
data to be enabled onto the MISO input line of the master. Master’s MOSI is enabled.
One half SCK period later, valid master data is transferred to the MOSI pin. Now that both
the master and slave data have been set, the SCK master clock pin goes HIGH after one
further half SCK period.
The data is now captured on the rising and propagated on the falling edges of the SCK
signal.
The CLK signal is forced LOW.
SSEL is forced HIGH.
The transmit MOSI/MISO pad is in high impedance.
SSEL
MOSI
MISO
SCK
4 to 16 bits
MSB
Rev. 04 — 26 August 2009
LSB
LSB
MSB
Figure
Q
20–97.
4 to 16 bits
Chapter 20: LPC24XX SSP interface SSP0/1
MSB
MSB
LSB
LSB
Q
4 to 16 bits
UM10237
© NXP B.V. 2009. All rights reserved.
LSB
LSB
Q
539 of 792

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