LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 645

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
UM10237_4
User manual
6.7 PWM Latch Enable Register (PWM0LER - 0xE001 4050 and PWM1LER
0xE001 8050)
The PWM Latch Enable registers are used to control the update of the PWM Match
registers when they are used for PWM generation. When software writes to the location of
a PWM Match register while the Timer is in PWM mode, the value is actually held in a
shadow register and not used immediately.
When a PWM Match 0 event occurs (normally also resetting the timer in PWM mode), the
contents of shadow registers will be transferred to the actual Match registers if the
corresponding bit in the Latch Enable register has been set. At that point, the new values
will take effect and determine the course of the next PWM cycle. Once the transfer of new
values has taken place, all bits of the LER are automatically cleared. Until the
corresponding bit in the PWMLER is set and a PWM Match 0 event occurs, any value
written to the PWM Match registers has no effect on PWM operation.
For example, if PWM is configured for double edge operation and is currently running, a
typical sequence of events for changing the timing would be:
The order of writing the two PWM Match registers is not important, since neither value will
be used until after the write to PWMLER. This insures that both values go into effect at the
same time, if that is required. A single value may be altered in the same way if needed.
The function of each of the bits in the PWMLER is shown in
Table 564: PWM Latch Enable Register (PWM0LER - address 0xE001 4050 and PWM1LER
Bit Symbol
0
1
2
3
4
•
•
•
•
Write a new value to the PWM Match1 register.
Write a new value to the PWM Match2 register.
Write to the PWMLER, setting bits 1 and 2 at the same time.
The altered values will become effective at the next reset of the timer (when a PWM
Match 0 event occurs).
Enable PWM
Match 0 Latch
Enable PWM
Match 1 Latch
Enable PWM
Match 2 Latch
Enable PWM
Match 3 Latch
Enable PWM
Match 4 Latch
address 0xE001 8050) bit description
Description
PWM MR0 register update control. Writing a one to this bit allows
the last value written to the PWM Match Register 0 to be become
effective when the timer is next reset by a PWM Match event. See
Section 25–6.4 “PWM Match Control Register (PWM0MCR -
0xE001 4014 and PWM1MCR 0xE001
PWM MR1 register update control. See bit 0 for details.
PWM MR2 register update control. See bit 0 for details.
PWM MR3 register update control. See bit 0 for details.
PWM MR4 register update control. See bit 0 for details.
Rev. 04 — 26 August 2009
Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1
8014)”.
Table
25–564.
UM10237
© NXP B.V. 2009. All rights reserved.
645 of 792
Reset
Value
0
0
0
0
0