LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 277
LPC2458FET180,551
Manufacturer Part Number
LPC2458FET180,551
Description
IC ARM7 MCU FLASH 512K 180TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2458FET180,551
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
136
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
180-TFBGA
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
32 bit
Data Ram Size
98 KB
Interface Type
CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
136
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 1 Channel
Package
180TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
For Use With
622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4258
935282454551
LPC2458FET180-S
935282454551
LPC2458FET180-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2458FET180,551
Manufacturer:
MICROCHIP
Quantity:
1 103
Company:
Part Number:
LPC2458FET180,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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UM10237_4
User manual
9.23.1 DMA access
9.22 Ethernet errors
9.23 AHB bandwidth
To do a full soft reset of the Ethernet block, device driver software must:
To reset just the transmit datapath, the device driver software has to:
To reset just the receive datapath, the device driver software has to:
The Ethernet block generates errors for the following conditions:
The Ethernet block is connected to an AHB bus which must carry all of the data and
control information associated with all Ethernet traffic in addition to the CPU accesses
required to operate the Ethernet block and deal with message contents.
Assumptions
By making some assumptions, the bandwidth needed for each type of AHB transfer can
be calculated and added in order to find the overall bandwidth requirement.
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RegReset: Resets all of the datapaths and registers in the host registers module,
excluding the registers in the MAC. A soft reset of the registers will also abort all AHB
transactions of the transmit and receive datapath. The reset bit will be cleared
autonomously by the Ethernet block.
Set the ‘SOFT RESET’ bit in the MAC1 register to 1.
Set the RegReset bit in the Command register, this bit clears automatically.
Reinitialize the MAC registers (0x000 to 0x0FC).
Reset the ‘SOFT RESET’ bit in the MAC1 register to 0.
Set the ‘RESET MCS/Tx’ bit in the MAC1 register to 1.
Disable the Tx DMA managers by setting the TxEnable bits in the Command register
to 0.
Set the TxReset bit in the Command register, this bit clears automatically.
Reset the ‘RESET MCS/Tx’ bit in the MAC1 register to 0.
Disable the receive function by resetting the ‘RECEIVE ENABLE’ bit in the MAC1
configuration register and resetting of the RxEnable bit of the Command register.
Set the ‘RESET MCS/Rx’ bit in the MAC1 register to 1.
Set the RxReset bit in the Command register, this bit clears automatically.
Reset the ‘RESET MCS/Rx’ bit in the MAC1 register to 0.
A reception can cause an error: AlignmentError, RangeError, LengthError,
SymbolError, CRCError, NoDescriptor, or Overrun. These are reported back in the
receive StatusInfo and in the interrupt status register (IntStatus).
A transmission can cause an error: LateCollision, ExcessiveCollision,
ExcessiveDefer, NoDescriptor, or Underrun. These are reported back in the
transmission StatusInfo and in the interrupt status register (IntStatus).
Rev. 04 — 26 August 2009
Chapter 11: LPC24XX Ethernet
UM10237
© NXP B.V. 2009. All rights reserved.
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