LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 470

IC ARM7 MCU FLASH 512K 180TFBGA

LPC2458FET180,551

Manufacturer Part Number
LPC2458FET180,551
Description
IC ARM7 MCU FLASH 512K 180TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets

Specifications of LPC2458FET180,551

Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
136
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
180-TFBGA
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
32 bit
Data Ram Size
98 KB
Interface Type
CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
136
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 1 Channel
Package
180TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
For Use With
622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
568-4258
935282454551
LPC2458FET180-S

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LPC2458FET180,551
Manufacturer:
MICROCHIP
Quantity:
1 103
Part Number:
LPC2458FET180,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
UM10237_4
User manual
Fig 74. Transmit buffer layout for standard and extended frame format configurations
31
31
TX
TX
0 0 0
TX Data 4
TX Data 8
TX Data 4
TX Data 8
6.3 Transmit Buffers (TXB)
6.4 Receive Buffer (RXB)
Frame info
Frame info
ID.28
The TXB represents a Triple Transmit Buffer, which is the interface between the Interface
Management Logic (IML) and the Bit Stream Processor (BSP). Each Transmit Buffer is
able to store a complete message which can be transmitted over the CAN network. This
buffer is written by the CPU and read out by the BSP.
The Receive Buffer (RXB) represents a CPU accessible Double Receive Buffer. It is
located between the CAN Controller Core Block and APB Interface Block and stores all
received messages from the CAN Bus line. With the help of this Double Receive Buffer
concept the CPU is able to process one message while another message is being
received.
The global layout of the Receive Buffer is very similar to the Transmit Buffer described
earlier. Identifier, Frame Format, Remote Transmission Request bit and Data Length
Code have the same meaning as described for the Transmit Buffer. In addition, the
Receive Buffer includes an ID Index field (see
The received Data Length Code represents the real transmitted Data Length Code, which
may be greater than 8 depending on transmitting CAN node. Nevertheless, the maximum
number of received data bytes is 8. This should be taken into account by reading a
message from the Receive Buffer. If there is not enough space for a new message within
the Receive Buffer, the CAN Controller generates a Data Overrun condition when this
message becomes valid and the acceptance test was positive. A message that is partly
written into the Receive Buffer (when the Data Overrun situation occurs) is deleted. This
situation is signalled to the CPU via the Status Register and the Data Overrun Interrupt, if
enabled.
24 23
24 23
0 . . . 0
unused
unused
TX Data 3
TX Data 7
TX Data 3
TX Data 7
TX DLC
TX DLC
Extended Frame Format (29-bit Identifier)
Standard Frame Format (11-bit Identifier)
16 15
16 15
...
Rev. 04 — 26 August 2009
TX Data 2
TX Data 6
TX Data 2
TX Data 6
unused
unused
8 7
8 7
ID.28 ... ID.18
Chapter 18: LPC24XX CAN controllers CAN1/2
TX Priority
TX Priority
TX Data 1
TX Data 5
TX Data 1
TX Data 5
ID.00
Section 18–8.9.1 “ID index
0
0
TDA
TDB
TDA
TDB
TFS
TFS
TID
TID
Descriptor
Data Field
Descriptor
Data Field
Field
Field
UM10237
© NXP B.V. 2009. All rights reserved.
field”).
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