LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 612

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
4. Pin descriptions
UM10237_4
User manual
next falling edge of the transmitting clock after a WS change. In stereo mode when WS is
low left data is transmitted and right data when WS is high. In mono mode the same data
is transmitted twice, once when WS is low and again when WS is high.
Table 530. Pin descriptions
Pin Name
I2SRX_CLK
I2SRX_WS
I2SRX_SDA
I2STX_CLK
I2STX_WS
I2STX_SDA
•
•
•
•
•
•
In master mode (ws_sel = 0), word select is generated internally with a 9 bit counter.
The half period count value of this counter can be set in the control register.
In slave mode (ws_sel = 1) word select is input from the relevant bus pin.
When an I
are sent continuously by the bus master, while data is sent continuously by the
transmitter.
Disabling the I
transmit and receive.
The stop bit will disable accesses by the transmit channel or the receive channel to
the FIFOs and will place the transmit channel in mute mode.
The mute control bit will place the transmit channel in mute mode. In mute mode, the
transmit channel FIFO operates normally, but the output is discarded and replaced by
zeroes. This bit does not affect the receive channel, data reception can occur
normally.
Type
Input/Output Receive Clock. A clock signal used to synchronize the transfer of
Input/Output Receive Word Select. Selects the channel from which data is to be
Input/Output Receive Data. Serial data, received MSB first. It is driven by the
Input/Output Transmit Clock. A clock signal used to synchronize the transfer of
Input/Output Transmit Data. Serial data, sent MSB first. It is driven by the
2
Input/Output Transmit Word Select. Selects the channel to which data is being
S bus is active, the word select, receive clock and transmit clock signals
2
S can be done with the stop or mute control bits separately for the
Rev. 04 — 26 August 2009
Description
data on the receive channel. It is driven by the master and received
by the slave. Corresponds to the signal SCK in the I
specification.
received. It is driven by the master and received by the slave.
Corresponds to the signal WS in the I
WS = 0 indicates that data is being received by channel 1 (left
channel).
WS = 1 indicates that data is being received by channel 2 (right
channel).
transmitter and read by the receiver. Corresponds to the signal SD
in the I
data on the transmit channel. It is driven by the master and received
by the slave. Corresponds to the signal SCK in the I
specification.
sent. It is driven by the master and received by the slave.
Corresponds to the signal WS in the I
WS = 0 indicates that data is being sent to channel 1 (left channel).
WS = 1 indicates that data is being sent to channel 2 (right channel).
transmitter and read by the receiver. Corresponds to the signal SD
in the I
2
2
S bus specification.
S bus specification.
Chapter 23: LPC24XX I
2
2
S bus specification.
S bus specification.
UM10237
© NXP B.V. 2009. All rights reserved.
2
2
S bus
S bus
2
S interface
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