LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 313

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
UM10237_4
User manual
7.9 Interrupt Mask register (LCD_INTMSK, RW - 0xFFE1 001C)
Table 267. LCD Control register (LCD_CTRL, RW - 0xFFE1 0018)
The LCD_INTMSK register controls whether various LCD interrupts occur.Setting bits in
this register enables the corresponding raw interrupt LCD_INTRAW status bit values to be
passed to the LCD_INTSTAT register for processing as interrupts.
The contents of the LCD_INTMSK register are described in
Table 268. Interrupt Mask register (LCD_INTMSK, RW - 0xFFE1 001C)
Bits
4
3:1
0
Bits
31:5
4
3
Function
LcdBW
LcdBpp
LcdEn
Function
reserved
BERIM
VCompIM
Rev. 04 — 26 August 2009
Description
STN LCD monochrome/color selection.
0 = STN LCD is color.
1 = STN LCD is monochrome.
This bit has no meaning in TFT mode.
LCD bits per pixel:
Selects the number of bits per LCD pixel:
000 = 1 bpp.
001 = 2 bpp.
010 = 4 bpp.
011 = 8 bpp.
100 = 16 bpp.
101 = 24 bpp (TFT panel only).
110 = 16 bpp, 5:6:5 mode.
111 = 12 bpp, 4:4:4 mode.
LCD enable control bit.
0 = LCD disabled. Signals LCDLP, LCDDCLK, LCDFP,
LCDENAB, and LCDLE are low.
1 = LCD enabled. Signals LCDLP, LCDDCLK, LCDFP,
LCDENAB, and LCDLE are high.
See LCD power-up and power-down sequence for details on
LCD power sequencing.
Description
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
AHB master error interrupt enable.
0: The AHB Master error interrupt is disabled.
1: Interrupt will be generated when an AHB Master error occurs.
Vertical compare interrupt enable.
0: The vertical compare time interrupt is disabled.
1: Interrupt will be generated when the vertical compare time (as
defined by LcdVComp field in the LCD_CTRL register) is
reached.
Chapter 12: LPC24XX LCD controller
Table
12–268.
UM10237
© NXP B.V. 2009. All rights reserved.
313 of 792
Reset
value
0x0
0x0
0x0
Reset
value
-
0x0
0x0