LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 689

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
UM10237_4
User manual
9.12 Read Boot code version number
9.13 Compare <address1> <address2> <no of bytes>
Table 616. LPC24xx part Identification numbers
In addition to the part identification numbers, the user can determine the device revision
by reading the register contents at address 0x0007 E070. The register value is encoded
as follows: 0x0 corresponds to revision ‘—’, 0x01 corresponds to revision A, 0x02
corresponds to revision B,..., 0x1A corresponds to revision Z. On all LPC24XX parts, this
feature is implemented starting with device revision C, so the register read will yield a
value of 0x03 (for revision C) or larger.
Table 617. ISP Read Boot Code version number command
Table 618. ISP Compare command
Device
LPC2458
LPC2468
LPC2478
Command
Input
Return Code CMD_SUCCESS followed by 2 bytes of boot code version number in ASCII format.
Description
Command
Input
Return Code CMD_SUCCESS | (Source and destination data are equal)
Description
Example
K
None
It is to be interpreted as <byte1(Major)>.<byte0(Minor)>.
This command is used to read the boot code version number.
M
Address1 (DST): Starting Flash or RAM address of data bytes to be compared.
This address should be a word boundary.
Address2 (SRC): Starting Flash or RAM address of data bytes to be compared.
This address should be a word boundary.
Number of Bytes: Number of bytes to be compared; should be a multiple of 4.
COMPARE_ERROR | (Followed by the offset of first mismatch)
COUNT_ERROR (Byte count is not a multiple of 4) |
ADDR_ERROR |
ADDR_NOT_MAPPED |
PARAM_ERROR |
This command is used to compare the memory contents at two locations.
Compare result may not be correct when source or destination address
contains any of the first 64 bytes starting from address zero. First 64 bytes
are re-mapped to Flash boot sector
"M 8192 1073741824 4<CR><LF>" compares 4 bytes from the RAM address
0x4000 0000 to the 4 bytes from the Flash address 0x2000.
ASCII/dec coding
352386869
369164085
386006837
Rev. 04 — 26 August 2009
Chapter 30: LPC24XX Flash memory programming firmware
Hex coding
0x1500 FF35
0x1600 FF35
0x1701 FF35
UM10237
© NXP B.V. 2009. All rights reserved.
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