LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 239
![IC ARM7 MCU FLASH 512K 180TFBGA](/photos/12/13/121378/180-tfbga_sml.jpg)
LPC2458FET180,551
Manufacturer Part Number
LPC2458FET180,551
Description
IC ARM7 MCU FLASH 512K 180TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2458FET180,551
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
136
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
180-TFBGA
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
32 bit
Data Ram Size
98 KB
Interface Type
CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
136
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 1 Channel
Package
180TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
For Use With
622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4258
935282454551
LPC2458FET180-S
935282454551
LPC2458FET180-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2458FET180,551
Manufacturer:
MICROCHIP
Quantity:
1 103
Company:
Part Number:
LPC2458FET180,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10237_4
User manual
7.4.2 Interrupt Enable Register (IntEnable - 0xFFE0 0FE4)
Table 228. Interrupt Status register (IntStatus - address 0xFFE0 0FE0) bit description
The interrupt status register is read-only. Setting can be done via the IntSet register. Reset
can be accomplished via the IntClear register.
The Interrupt Enable register (IntEnable) has an address of 0xFFE0 0FE4. The interrupt
enable register bit definition is shown in
Table 229. Interrupt Enable register (intEnable - address 0xFFE0 0FE4) bit description
Bit
0
1
2
3
4
5
6
7
11:8
12
13
31:14
Bit
0
1
2
3
Symbol
RxOverrunInt
RxErrorInt
RxFinishedInt
RxDoneInt
TxUnderrunInt Interrupt set on a fatal underrun error in the transmit queue. The
TxErrorInt
TxFinishedInt
TxDoneInt
-
SoftInt
WakeupInt
-
Symbol
RxOverrunIntEn
RxErrorIntEn
RxFinishedIntEn
RxDoneIntEn
Rev. 04 — 26 August 2009
Function
Interrupt set on a fatal overrun error in the receive queue. The
fatal interrupt should be resolved by a Rx soft-reset. The bit is not
set when there is a nonfatal overrun error.
Interrupt trigger on receive errors: AlignmentError, RangeError,
LengthError, SymbolError, CRCError or NoDescriptor or Overrun.
Interrupt triggered when all receive descriptors have been
processed i.e. on the transition to the situation where
ProduceIndex == ConsumeIndex.
Interrupt triggered when a receive descriptor has been processed
while the Interrupt bit in the Control field of the descriptor was set.
fatal interrupt should be resolved by a Tx soft-reset. The bit is not
set when there is a nonfatal underrun error.
Interrupt trigger on transmit errors: LateCollision,
ExcessiveCollision and ExcessiveDefer, NoDescriptor or
Underrun.
Interrupt triggered when all transmit descriptors have been
processed i.e. on the transition to the situation where
ProduceIndex == ConsumeIndex.
Interrupt triggered when a descriptor has been transmitted while
the Interrupt bit in the Control field of the descriptor was set.
Unused
Interrupt triggered by software writing a 1 to the SoftintSet bit in
the IntSet register.
Interrupt triggered by a Wakeup event detected by the receive
filter.
Unused
Function
Enable for interrupt trigger on receive buffer overrun or
Enable for interrupt triggered when all receive descriptors have
Enable for interrupt triggered when a receive descriptor has
descriptor underrun situations.
Enable for interrupt trigger on receive errors.
been processed i.e. on the transition to the situation where
ProduceIndex == ConsumeIndex.
been processed while the Interrupt bit in the Control field of the
descriptor was set.
Table
11–229.
Chapter 11: LPC24XX Ethernet
UM10237
© NXP B.V. 2009. All rights reserved.
239 of 792
Reset
value
0
0
0
0
0
0
0
0
0x0
0
0
0x0
Reset
value
0
0
0
0
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