LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 672
LPC2458FET180,551
Manufacturer Part Number
LPC2458FET180,551
Description
IC ARM7 MCU FLASH 512K 180TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2458FET180,551
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
136
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
180-TFBGA
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
32 bit
Data Ram Size
98 KB
Interface Type
CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
136
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 1 Channel
Package
180TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
For Use With
622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4258
935282454551
LPC2458FET180-S
935282454551
LPC2458FET180-S
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2458FET180,551
Manufacturer:
MICROCHIP
Quantity:
1 103
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Part Number:
LPC2458FET180,551
Manufacturer:
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UM10237_4
User manual
5.4 A/D Interrupt Enable Register (AD0INTEN - 0xE003 400C)
5.5 A/D Data Registers (AD0DR0 to AD0DR7 - 0xE003 4010 to
This register allows control over which A/D channels generate an interrupt when a
conversion is complete. For example, it may be desirable to use some A/D channels to
monitor sensors by continuously performing conversions on them. The most recent
results are read by the application program whenever they are needed. In this case, an
interrupt is not desirable at the end of each conversion for some A/D channels.
Table 596: A/D Interrupt Enable Register (AD0INTEN - address 0xE003 400C) bit description
0xE003 402C)
The A/D Data Register hold the result when an A/D conversion is complete, and also
include the flags that indicate when a conversion has been completed and when a
conversion overrun has occurred.
Table 597: A/D Data Registers (AD0DR0 to AD0DR7 - addresses 0xE003 4010 to
Bit
7:0
8
31:9 Unused
Bit
5:0
15:6
29:16 Unused
30
31
Symbol
ADINTEN 7:0 These bits allow control over which A/D channels generate
ADGINTEN
Symbol
Unused
V/V
OVERRUN This bit is 1 in burst mode if the results of one or more conversions
DONE
REF
0xE003 402C) bit description
Description
Unused, always 0.
These bits always read as zeroes. They provide compatible expansion
room for future, higher-resolution ADCs.
When DONE is 1, this field contains a binary fraction representing the
voltage on the Ain pin, divided by the voltage on the Vref pin. Zero in
the field indicates that the voltage on the Ain pin was less than, equal
to, or close to that on V
Ain was close to, equal to, or greater than that on Vref.
These bits always read as zeroes. They allow accumulation of
successive A/D values without AND-masking, for at least 256 values
without overflow into the CHN field.
was (were) lost and overwritten before the conversion that produced
the result in the LS bits.This bit is cleared by reading this register.
This bit is set to 1 when an A/D conversion completes. It is cleared
when this register is read.
Description
interrupts for conversion completion. When bit 0 is one, completion
of a conversion on A/D channel 0 will generate an interrupt, when bit
1 is one, completion of a conversion on A/D channel 1 will generate
an interrupt, etc.
When 1, enables the global DONE flag in ADDR to generate an
interrupt. When 0, only the individual A/D channels enabled by
ADINTEN 7:0 will generate interrupts.
Unused, always 0.
Rev. 04 — 26 August 2009
Chapter 28: LPC24XX Analog-to Digital Converter (ADC)
REF
, while 0x3FF indicates that the voltage on
UM10237
© NXP B.V. 2009. All rights reserved.
672 of 792
Reset
Value
0x00
1
0
Reset
Value
0
NA
0
0
0
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