LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 739

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
11. Flow control
UM10237_4
User manual
Note: Memory-to-memory transfers should be programmed with a low channel priority,
otherwise other DMA channels cannot access the bus until the memory-to-memory
transfer has finished, or other AHB masters cannot perform any transaction.
The peripheral that controls the length of the packet is known as the flow controller. The
flow controller is usually the GPDMA where the packet length is programmed by software
before the DMA channel is enabled. If the packet length is unknown when the DMA
channel is enabled, either the source or destination peripherals can be used as the flow
controller.
For simple or low-performance peripherals that know the packet length (that is, when the
peripheral is the flow controller), a simple way to indicate that a transaction has completed
is for the peripheral to generate an interrupt and enable the processor to reprogram the
DMA channel.
The transfer size value (in the DMACCxControl register) is ignored if a peripheral is
configured as the flow controller.
When the DMA is transferred:
1. The GPDMA issues an acknowledge to the peripheral in order to indicate that the
2. A TC interrupt is generated, if enabled.
3. The GPDMA moves on to the next LLI.
transfer has finished.
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
Rev. 04 — 26 August 2009
UM10237
© NXP B.V. 2009. All rights reserved.
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