LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 367

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
UM10237_4
User manual
11.7 Get Device Status (Command: 0xFE, Data: read 1 byte)
11.8 Get Error Code (Command: 0xFF, Data: read 1 byte)
Table 351. Set Device Status Register bit description
The Get Device Status command returns the Device Status Register. Reading the device
status returns 1 byte of data. The bit field definition is same as the Set Device Status
Register as shown in
Remark: To ensure correct operation, the DEV_STAT bit of USBDevIntSt must be cleared
before executing the Get Device Status command.
Different error conditions can arise inside the SIE. The Get Error Code command returns
the last error code that occurred. The 4 least significant bits form the error code.
Bit Symbol
3
4
7:5 -
SUS_CH
RST
Value Description
0
1
0
1
Table
Rev. 04 — 26 August 2009
Suspend (SUS) bit change indicator. The SUS bit can toggle
because:
This bit is cleared when read.
SUS bit not changed.
SUS bit changed. At the same time a DEV_STAT interrupt is
generated.
Bus Reset bit. On a bus reset, the device will automatically go to
the default state. In the default state:
Note: Bus resets are ignored when the device is not connected
(CON=0).
This bit is cleared when read.
This bit is set when the device receives a bus reset. A DEV_STAT
interrupt is generated.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
•
•
•
•
•
•
•
•
•
•
•
The device goes into the suspended state.
The device is disconnected.
The device receives resume signalling on its upstream port.
Device is unconfigured.
Will respond to address 0.
Control endpoint will be in the Stalled state.
All endpoints are unrealized except control endpoints EP0
and EP1.
Data toggling is reset for all endpoints.
All buffers are cleared.
There is no change to the endpoint interrupt status.
DEV_STAT interrupt is generated.
13–351.
Chapter 13: LPC24XX USB device controller
UM10237
© NXP B.V. 2009. All rights reserved.
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Reset
value
0
0
NA