LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 60

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
UM10237_4
User manual
3.4.1 Idle mode
3.4.2 Sleep mode
3.4 Power control
Table 58.
[1]
The LPC2400 supports a variety of power control features. There are four special modes
of processor power reduction: Idle mode, Sleep mode, Power-down mode, and Deep
power-down mode. The CPU clock rate may also be controlled as needed by changing
clock sources, re-configuring PLL values, and/or altering the CPU clock divider value. This
allows a trade-off of power versus processing speed based on application requirements.
In addition, Peripheral Power Control allows shutting down the clocks to individual on-chip
peripherals, allowing fine tuning of power consumption by eliminating all dynamic power
use in any peripherals that are not required for the application.
The LPC2400 also implements a separate power domain in order to allow turning off
power to the bulk of the device while maintaining operation of the Real Time Clock and a
small static RAM, referred to as the Battery RAM. This feature is described in more detail
later in this chapter under the heading Power Domains, and in the Real Time Clock and
Battery RAM chapter.
When Idle mode is entered, the clock to the core is stopped. Resumption from the Idle
mode does not need any special sequence but re-enabling the clock to the ARM core.
In Idle mode, execution of instructions is suspended until either a Reset or interrupt
occurs. Peripheral functions continue operation during Idle mode and may generate
interrupts to cause the processor to resume execution. Idle mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
When the chip enters the Sleep mode, the main oscillator is powered down and all clocks
are stopped. The output of the IRC is disabled but the IRC is not powered down for a fast
wakeup later. The 32 kHz RTC oscillator is not stopped because the RTC interrupts may
be used as the wakeup source. The flash is left in the standby mode allowing a very quick
wakeup. The PLL is automatically turned off and disconnected. The CCLK and USBCLK
clock dividers automatically get reset to zero.
PCLKSEL0 and PCLKSEL1
individual peripheral’s clock
select options
00
01
10
11
For PCLK_RTC only, the value ’01’ is illegal. Do not write ’01’ to the PCLK_RTC. Attempting to write ’01’
results in the previous value being unchanged.
Peripheral Clock Selection register bit values
Rev. 04 — 26 August 2009
Function
PCLK_xyz = CCLK/4
PCLK_xyz = CCLK
PCLK_xyz = CCLK/2
Peripheral’s clock is selected to PCLK_xyz = CCLK/8
except for CAN1, CAN2, and CAN filtering when ’11’
selects PCLK_xyz = CCLK/6.
Chapter 4: LPC24XX Clocking and power control
[1]
UM10237
© NXP B.V. 2009. All rights reserved.
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Reset
value
00