LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 791

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
4.2.8
4.2.9
4.2.10
4.2.11
4.2.12
4.2.13
4.3
5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
6
6.1
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
6.1.8
6.1.9
6.1.10
Chapter 33: LPC24XX EmbeddedICE
1
2
3
4
Chapter 34: LPC24XX Embedded Trace Module (ETM)
1
2
3
3.1
4
UM10237_4
User manual
Programming the GPDMA. . . . . . . . . . . . . . . 718
Register description . . . . . . . . . . . . . . . . . . . 720
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 740
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 741
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 744
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 745
Endian behavior . . . . . . . . . . . . . . . . . . . . . . 714
Error conditions . . . . . . . . . . . . . . . . . . . . . . 716
Channel hardware . . . . . . . . . . . . . . . . . . . . 717
DMA request priority . . . . . . . . . . . . . . . . . . . 717
Interrupt generation . . . . . . . . . . . . . . . . . . . 717
The completion of the DMA transfer
indication . . . . . . . . . . . . . . . . . . . . . . . . . . . 717
DMA system connections . . . . . . . . . . . . . . . 717
Enabling the GPDMA . . . . . . . . . . . . . . . . . . 718
Disabling the GPDMA. . . . . . . . . . . . . . . . . . 718
Enabling a DMA channel . . . . . . . . . . . . . . . 719
Disabling a DMA channel . . . . . . . . . . . . . . . 719
Disabling a DMA channel without losing data in
the FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
Setup a new DMA transfer . . . . . . . . . . . . . . 719
Disabling a DMA channel and losing data in the
FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
Halting a DMA transfer . . . . . . . . . . . . . . . . . 719
Programming a DMA channel. . . . . . . . . . . . 720
General GPDMA registers . . . . . . . . . . . . . . 721
Interrupt Status Register (DMACIntStatus -
0xFFE0 4000) . . . . . . . . . . . . . . . . . . . . . . . . 721
Interrupt Terminal Count Status Register
(DMACIntTCStatus - 0xFFE0 4004) . . . . . . . 722
Interrupt Terminal Count Clear Register
(DMACIntClear - 0xFFE0 4008) . . . . . . . . . . 722
Interrupt Error Status Register
(DMACIntErrorStatus - 0xFFE0 400C) . . . . . 722
Interrupt Error Clear Register (DMACIntErrClr -
0xFFE0 4010) . . . . . . . . . . . . . . . . . . . . . . . . 723
Raw Interrupt Terminal Count Status Register
(DMACRawIntTCStatus - 0xFFE0 4014) . . . 723
Raw Error Interrupt Status Register
(DMACRawIntErrorStatus - 0xFFE0 4018). . 723
Enabled Channel Register (DMACEnbldChns -
0xFFE0 401C) . . . . . . . . . . . . . . . . . . . . . . . 724
Software Burst Request Register
(DMACSoftBReq - 0xFFE0 4020). . . . . . . . . 724
Software Single Request Register
(DMACSoftSReq - 0xFFE0 4024). . . . . . . . . 725
ETM configuration . . . . . . . . . . . . . . . . . . . . 744
Rev. 04 — 26 August 2009
6.1.11
6.1.12
6.1.13
6.1.14
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
7
8
8.1
8.2
8.3
9
9.1
9.2
10
10.1
10.2
10.3
11
5
6
7
5
6
7
Chapter 36: LPC24XX Supplementary information
Address generation . . . . . . . . . . . . . . . . . . . 733
Scatter/Gather . . . . . . . . . . . . . . . . . . . . . . . . 733
Interrupt requests . . . . . . . . . . . . . . . . . . . . . 735
GPDMA data flow . . . . . . . . . . . . . . . . . . . . . 736
Flow control. . . . . . . . . . . . . . . . . . . . . . . . . . 739
JTAG function select. . . . . . . . . . . . . . . . . . . 742
Register description . . . . . . . . . . . . . . . . . . . 742
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . 742
Register description . . . . . . . . . . . . . . . . . . . 745
Reset state of multiplexed pins . . . . . . . . . . 746
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . 747
Software Last Burst Request Register
(DMACSoftLBreq - 0xFFE0 4028) . . . . . . . . 725
Software Last Single Request Register
(DMACSoftLSReq - 0xFFE0 402C) . . . . . . . 725
Configuration Register (DMACConfiguration -
0xFFE0 4030) . . . . . . . . . . . . . . . . . . . . . . . 726
Synchronization Register (DMACSync -
0xFFE0 4034) . . . . . . . . . . . . . . . . . . . . . . . 726
Channel registers. . . . . . . . . . . . . . . . . . . . . 727
Channel Source Address Registers
(DMACC0SrcAddr - 0xFFE0 4100 and
DMACC1SrcAddr - 0xFFE0 4120). . . . . . . . 727
Channel Destination Address Registers
(DMACC0DestAddr - 0xFFE0 4104 and
DMACC1DestAddr - 0xFFE0 4124). . . . . . . 727
Channel Linked List Item Registers (DMACC0LLI
- 0xFFE0 4108 and DMACC1LLI -
0xFFE0 4128) . . . . . . . . . . . . . . . . . . . . . . . 728
Channel Control Registers (DMACC0Control -
0xFFE0 410C and DMACC0Control -
0xFFE0 412C) . . . . . . . . . . . . . . . . . . . . . . . 728
Protection and Access Information . . . . . . . 730
Channel Configuration Registers
(DMACC0Configuration - 0xFFE0 4110 and
DMACC1Configuration - 0xFFE0 4130) . . . 731
Lock control . . . . . . . . . . . . . . . . . . . . . . . . . 732
Flow control and transfer type . . . . . . . . . . . 733
Linked List Items . . . . . . . . . . . . . . . . . . . . . 733
Programming the GPDMA for scatter/gather DMA
734
Example of scatter/gather DMA . . . . . . . . . . 734
Hardware interrupt sequence flow . . . . . . . . 736
Interrupt polling sequence flow . . . . . . . . . . 736
Peripheral-to-memory, or Memory-to-peripheral
DMA flow . . . . . . . . . . . . . . . . . . . . . . . . . . . 737
Peripheral-to-peripheral DMA flow. . . . . . . . 737
Memory-to-memory DMA flow . . . . . . . . . . . 738
UM10237
© NXP B.V. 2009. All rights reserved.
791 of 792