LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 86

IC ARM7 MCU FLASH 512K 180TFBGA

LPC2458FET180,551

Manufacturer Part Number
LPC2458FET180,551
Description
IC ARM7 MCU FLASH 512K 180TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets

Specifications of LPC2458FET180,551

Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
136
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
180-TFBGA
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
32 bit
Data Ram Size
98 KB
Interface Type
CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
136
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 1 Channel
Package
180TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
For Use With
622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
568-4258
935282454551
LPC2458FET180-S

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LPC2458FET180,551
Manufacturer:
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Quantity:
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Part Number:
LPC2458FET180,551
Manufacturer:
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NXP Semiconductors
UM10237_4
User manual
10.14 Dynamic Memory Auto-refresh Period register (EMCDynamictRFC -
10.15 Dynamic Memory Exit Self-refresh register (EMCDynamictXSR -
Table 80.
0xFFE0 804C)
The EMCDynamicTRFC register enables you to program the auto-refresh period, and
auto-refresh to active command period, tRFC. It is recommended that this register is
modified during system initialization, or when there are no current or outstanding
transactions. This can be ensured by waiting until the EMC is idle, and then entering
low-power, or disabled mode. This value is normally found in SDRAM data sheets as
tRFC, or sometimes as tRC. This register is accessed with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 5–81
Table 81.
0xFFE0 8050)
The EMCDynamicTXSR register enables you to program the exit self-refresh to active
command time, tXSR. It is recommended that this register is modified during system
initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode.
This value is normally found in SDRAM data sheets as tXSR. This register is accessed
with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 5–82
Bit
4:0
31:5
Bit
4:0
31:5
Symbol
Active to active
command
period (tRC)
-
Symbol
Auto-refresh
period and
auto-refresh to
active command
period (tRFC)
-
Dynamic Mempry Active to Active Command Period register (EMCDynamictRC -
address 0xFFE0 8048) bit description
Dynamic Memory Auto-refresh Period register (EMCDynamictRFC - address
0xFFE0 804C) bit description
shows the bit assignments for the EMCDynamicTRFC register.
shows the bit assignments for the EMCDynamicTXSR register.
Rev. 04 — 26 August 2009
Value Description
0x0 -
0x1E
0xF
Value Description
0x0 -
0x1E
0xF
-
-
Chapter 5: LPC24XX External Memory Controller (EMC)
n + 1 clock cycles. The delay is in CCLK cycles.
32 clock cycles (POR reset value).
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
n + 1 clock cycles. The delay is in CCLK cycles.
32 clock cycles (POR reset value).
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
UM10237
© NXP B.V. 2009. All rights reserved.
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Reset
Value
0x1F
NA
Reset
Value
0x1F
NA

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