LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 175

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] Pad provides special analog functionality.
[11] Pad provides special analog functionality.
[12] Pad provides special analog functionality.
[13] Pad provides special analog functionality.
[14] Pad provides special analog functionality.
[15] Either the I
[16] Either the USB OTG function or the LCD function is selectable.
[17] Either the trace function or the LCD function is selectable.
[18] Either one of the external interrupts EINT1 to EINT3 or the LCD function is selectable.
[19] Either one of the timer outputs MAT2[1] and MAT2[0] or the LCD function is selectable.
6. LPC2420/60/70 boot control
UM10237_4
User manual
5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.
5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input,
digital section of the pad is disabled.
5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output,
digital section of the pad is disabled.
Open-drain 5 V tolerant digital I/O pad, compatible with I
functionality. When power is switched off, this pin connected to the I
configuration applies to all functions on this pin.
Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and
Low-speed mode only).
5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis.
5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.
Pad provides special analog functionality.
Pad provides special analog functionality.
2
S function or the LCD function is selectable.
The flashless LPC2420, LPC2460, and LPC2470 use pins P3[15]/D15 and P3[14]/D14 for
configuring the external memory bus during the boot process. These pins are sampled
during Power-on Reset (POR). See
pins.
Table 125. Boot control on pins P3[15]/D15 and P3/14]/D14
During the boot process, external memory banks 0 and 1 are configured with the same
data bus width determined by the setting of the two boot pins P3[15]/D15 and P3[14]/D14.
Unused address pins (A0 when booting from 16-bit wide external memory, A1 and A0
when booting from 32-bit wide memory) are configured as GPIO.
The boot loader remaps the vector table to external memory (see
0x3) and branches to address 0x0. The external boot memory must be connected to chip
select 1 (CS1). Note that CS1 is mirrored onto CS0 because the address mirror bit is set
P3[15]/D15
BOOT1
0
0
1
1
P3[14]/D14 Description
BOOT0
0
1
0
1
Rev. 04 — 26 August 2009
Boot from 8-bit external memory on CS1. Sampled on POR signal.
Reserved. Do not use.
Boot from 32-bit external memory on CS1. Sampled on POR signal.
Boot from 16-bit external memory on CS1. Sampled on POR signal.
2
C-bus 400 kHz specification. It requires an external pull-up to provide output
2
Table 8–125
C-bus is floating and does not disturb the I
Chapter 8: LPC24XX Pin configuration
for possible settings of the boot control
Table
UM10237
2
© NXP B.V. 2009. All rights reserved.
C lines. Open-drain
2–21, MEMAP =
175 of 792