DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 973

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Parameter Settings
Table 1–2. MegaWizard Plug-In Manager Options (PLL/Ports Screen) (Part 2 of 3)
February 2011 Altera Corporation
Enable PLL phase frequency
detector (PFD) feedback to
compensate latency
uncertainty in tx_dataout
and tx_clkout paths
relative to the reference
clock.
What is the TX PLL
bandwidth mode?
What is the receiver CDR
bandwidth mode?
What is the acceptable PPM
threshold between the
receiver CDR VCO and the
receiver input reference
clock?
Optional Ports
Create a gxb_powerdown
port to power down the
transceiver block.
Create a pll_powerdown
port to power down the TX
PLL.
Create a rx_analogreset
port for the analog portion of
the receiver.
ALTGX Setting
This option applies only when you select
Deterministic Latency functional mode.
The available options are Auto, Low, Medium, and
High. Select the appropriate option based on your
system requirements.
The available options are Auto, Low, Medium, and
High. Select the appropriate option based on your
system requirements.
In Automatic Lock mode, the CDR remains in
Lock-to-Data (LTD) mode as long as the parts per
million (PPM) difference between the CDR VCO
output clock and the input reference clock is less
than the PPM value that you set in this option. If the
PPM difference is greater than the PPM value that
you set in this option, the CDR switches to
Lock-to-Reference (LTR) mode.
The range of values available in this option is
±62.5 ppm to ±1000 ppm.
When asserted, this signal powers down the entire
transceiver block. If none of the channels are
instantiated in a transceiver block, the Quartus II
software automatically powers down the entire
transceiver block.
Each transceiver block has two CMU PLLs. Each
CMU/ATX PLL has a dedicated power down signal
called pll_powerdown. This signal powers down
the CMU/ATX PLL.
The receiver analog reset port is available in
Receiver only and Receiver and Transmitter
operation modes. This resets part of the analog
portion of the receiver CDR in the receiver channel.
Altera recommends using this port to implement
the recommended reset sequence. The minimum
pulse width is two parallel clock cycles.
Description
(1)
“CMU PLL Feedback” section in the
Transceiver Architecture in Stratix IV
Devices
“PLL Bandwidth Setting” section in
the
Stratix IV Devices
and Switching Characteristics for
Stratix IV Devices
“Clock and Data Recovery Unit”
section in the
in Stratix IV Devices
DC and Switching Characteristics for
Stratix IV Devices
“Automatic Lock Mode” section in the
Transceiver Architecture in Stratix IV
Devices
“User Reset and Power Down
Signals” section in the
and Power Down in Stratix IV Devices
chapter.
“User Reset and Power Down
Signals” section in the
and Power Down in Stratix IV Devices
chapter.
“User Reset and Power Down
Signals” in the
Power Down in Stratix IV Devices
chapter.
Transceiver Architecture in
Stratix IV Device Handbook Volume 3
chapter.
chapter.
Reference
Transceiver Architecture
Reset Control and
chapter and the
section.
section.
chapter and the
Reset Control
Reset Control
DC
1–15