DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 653

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Port Lists
Transceiver Port Lists
Table 1–73. Stratix IV GX and GT ALTGX Megafunction Ports: Transmitter Ports (Part 1 of 3)
February 2011 Altera Corporation
Transmitter Phase Compensation FIFO
tx_datain
tx_clkout
tx_coreclk
tx_phase_comp_fifo_
error
Port Name
Instantiate the Stratix IV GX and GT transceivers using the ALTGX megafunction
instance in the Quartus II MegaWizard Plug-In Manager. The ALTGX megafunction
instance allows you to configure transceivers for your intended protocol and select
optional control and status ports to and from the instantiated transceiver channels.
Table 1–73
ports.
Table 1–73
Output
Output
Output
Input/
Input
Input
through
lists the ALTGX megafunction transmitter ports.
modes. coreclk
Synchronous to
Synchronous to
Table 1–79
tx_clkout for
tx_clkout or
Clock Domain
coreclkout.
tx_clkout/
coreclkout
clock signal.
non-bonded
Clock signal
Clock signal
for bonded
modes.
list a brief description of the ALTGX megafunction
Parallel data input from the FPGA fabric to the
transmitter.
■
FPGA fabric-transceiver interface clock.
■
■
■
Optional write clock port for the transmitter
phase compensation FIFO.
■
■
Transmitter phase compensation FIFO full or
empty indicator.
■
Bus width—depends on the channel width
multiplied by the number of channels per
instance.
Bonded channel configurations—not
available.
Non-bonded channel configurations—each
channel has a tx_clkout signal.
Use this clock signal to clock the parallel
data tx_datain from the FPGA fabric into
the transmitter.
If not selected—the Quartus II software
automatically selects
tx_clkout/coreclkout as the write clock
for transmitter phase compensation FIFO.
If selected—you must drive this port with a
clock that is frequency locked to
tx_clkout/coreclkout.
A high level—the transmitter phase
compensation FIFO is either full or empty.
Stratix IV Device Handbook Volume 2: Transceivers
Description
Channel
Channel
Channel
Channel
Scope
1–209