DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 147
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 147 of 1154
- Download datasheet (32Mb)
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
Figure 5–26. ZDB Mode in Stratix IV PLLs
Note to
(1) The bidirectional I/O pin must be assigned to the PLL_<#>_FB_CLKOUT0p pin for left and right PLLs and to the PLL_<#>_FBp_/CLKOUT1 pin for
February 2011 Altera Corporation
top and bottom PLLs.
Figure
5–26:
1
inclk
When using ZDB mode, to avoid signal reflection, do not place board traces on the
bi-directional I/O pin.
Figure 5–27
ZDB mode.
Figure 5–27. Phase Relationship Between the PLL Clocks in ZDB Mode
Note to
(1) The internal PLL clock output can lead or lag the external PLL clock outputs.
External Feedback Mode
In external feedback mode, the external feedback input pin (fbin) is phase-aligned
with the clock input pin, as shown in
remove clock delay and skew between devices. This mode is supported on all
Stratix IV PLLs.
In external feedback mode, the output of the M counter (FBOUT) feeds back to the PLL
fbin input (using a trace on the board) becoming part of the feedback loop. Also, use
one of the dual-purpose external clock outputs as the fbin input pin in this mode.
When using external feedback mode, you must use the same I/O standard on the
input clock, feedback input, and output clocks. Left and right PLLs support this mode
when using single-ended I/O standards only.
÷n
Figure
5–27:
shows an example waveform of the PLL clocks’ phase relationship in
PLL Clock at the
Register Clock Port (1)
PFD
Dedicated PLL
Clock Outputs
PLL Reference
Clock at the
Input Pin
CP/LF
Phase Aligned
VCO
Figure
÷C0
÷C1
÷m
5–28. Aligning these clocks allows you to
fbout
fbin
PLL_<#>_CLKOUT#
PLL_<#>_CLKOUT#
Stratix IV Device Handbook Volume 1
bidirectional
I/O pin (1)
5–31
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