DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 744

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

2–72
Table 2–18. Quartus II Assignments
Using the CMU/ATX PLL for Clocking User Logic in the FPGA Fabric
Stratix IV Device Handbook Volume 2: Transceivers
From
To
Assignment Name
Value
Note to
(1) You can find the full hierarchy name of the 0 PPM clock driver using the Node Finder feature in the Quartus II Assignment Editor.
Table
2–18:
1
You must ensure that the clock driver for all the connected rx_coreclk ports has a
0 PPM difference with respect to the FIFO write clock in those channels.
Table 2–18
For more implementation details, refer to
Sixteen Channels Across Four Transceiver Blocks” on page
Basic (PMA Direct) Mode
In Basic (PMA Direct) mode, each channel must be clocked by its own rx_clkout. As a
result, the number of global and/or regional clock resources required is significantly
higher. Bonding is not supported for receivers configured in Basic (PMA Direct)
functional mode.
Some designs that use multiple clock domains may run out of PLLs in the FPGA
fabric. In such a scenario, if your design has CMU or ATX PLLs that are not being
used, it may be possible to use them for clocking user logic in the FPGA fabric.
However, the CMU PLLs and ATX PLLs do not have many features that are
supported by the PLLs in the FPGA fabric.
The following are the supported features on CMU PLLs and ATX PLLs used as PLLs
for clocking user logic in the FPGA fabric:
■
■
■
■
Full design hierarchy name of one of the following clock drivers that you choose to drive the
rx_coreclk ports of all identical channels (1):
■
■
■
■
■
■
■
rx_datain pins of all channels whose rx_coreclk ports are connected together and driven by
the 0 PPM clock driver.
GXB 0 PPM Core Clock Setting
ON
Single clock output
Programmable PLL bandwidth
PLL PFD power down control
Lock status signal
tx_clkout
rx_clkout
coreclkout
FPGA CLK input pins
Transceiver refclk pins
Clock output from the left and right or top and bottom PLLs
tx_dataout port of one of the identical channels
lists the Quartus II assignments that you must make.
Using the CMU/ATX PLL for Clocking User Logic in the FPGA Fabric
“Configuration Example 3: Configuring
Chapter 2: Transceiver Clocking in Stratix IV Devices
2–77.
February 2011 Altera Corporation