DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 661

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Port Lists
Table 1–74. Stratix IV GX and GT ALTGX Megafunction Ports: Receiver Ports (Part 6 of 7)
February 2011 Altera Corporation
rx_coreclk
rx_phase_comp_fifo_
error
Receiver Physical Media Attachment (PMA)
rx_datain
rx_cruclk
rx_pll_locked
rx_freqlocked
rx_locktodata
Port Name
Output
Output
Output
Output
Input/
Input
Input
Input
Input
coreclkout for
Synchronous to
bonded modes.
tx_clkout for
tx_clkout or
Asynchronous
Asynchronous
Asynchronous
Clock Domain
coreclkout.
Clock signal
non-bonded
Clock signal
modes.
signal
signal
signal
N/A
Optional read clock port for the receiver phase
compensation FIFO.
■
■
Receiver phase compensation FIFO full or
empty indicator.
■
Receiver serial data input port.
Input reference clock for the receiver clock and
data recovery.
Receiver CDR lock-to-reference indicator.
■
■
Receiver CDR lock mode indicator.
■
■
Receiver CDR lock-to-data mode control signal.
■
■
If not selected—the Quartus II software
automatically selects
rx_clkout/tx_clkout/
coreclkout as the read clock for the
receiver phase compensation FIFO.
If selected—drive this port with a clock that
has 0 PPM difference with respect to
rx_clkout/tx_clkout/
coreclkout.
A high level—the receiver phase
compensation FIFO is either full or empty.
A high level—the receiver CDR is locked to
the input reference clock.
A low level—the receiver CDR is not locked
to the input reference clock.
A high level—the receiver CDR is in
lock-to-data mode.
A low level—the receiver CDR is in
lock-to-reference mode.
When asserted high—the receiver CDR is
forced to lock-to-data mode.
When de-asserted low—the receiver CDR
lock mode depends on the
rx_locktorefclk signal level.
Stratix IV Device Handbook Volume 2: Transceivers
Description
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Scope
1–217