DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 279

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off.
and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
SIV51008-3.2
Overview
Stratix IV Device Handbook Volume 1
February 2011
February 2011
SIV51008-3.2
This chapter describes the significant advantages of the high-speed differential I/O
interfaces and the dynamic phase aligner (DPA) over single-ended I/Os and their
contribution to the overall system bandwidth achievable with Stratix
references to Stratix IV devices in this chapter apply to Stratix IV E, GT, and GX
devices.
The Stratix IV device family consists of the Stratix IV E (Enhanced) devices without
high-speed clock data recovery (CDR) based transceivers, Stratix IV GT devices with
up to 48 CDR-based transceivers running up to 11.3 Gbps, and Stratix IV GX devices
with up to 48 CDR-based transceivers running up to 8.5 Gbps.
The following sections describe the Stratix IV high-speed differential I/O interfaces
and DPA:
■
■
■
■
■
■
■
■
■
■
■
All Stratix IV E, GX, and GT devices have built-in serializer/deserializer (SERDES)
circuitry that supports high-speed LVDS interfaces at data rates of up to 1.6 Gbps.
SERDES circuitry is configurable to support source-synchronous communication
protocols such as Utopia, Rapid I/O, XSBI, small form factor interface (SFI), serial
peripheral interface (SPI), and asynchronous protocols such as SGMII and Gigabit
Ethernet.
The Stratix IV device family has the following dedicated circuitry for high-speed
differential I/O support:
■
■
■
“Locations of the I/O Banks” on page 8–3
“LVDS Channels” on page 8–4
“LVDS SERDES” on page 8–8
“ALTLVDS Port List” on page 8–9
“Differential Transmitter” on page 8–11
“Differential Receiver” on page 8–17
“LVDS Interface with the Use External PLL Option Enabled” on page 8–26
“Left and Right PLLs (PLL_Lx and PLL_Rx)” on page 8–29
“Stratix IV Clocking” on page 8–30
“Source-Synchronous Timing Budget” on page 8–31
“Differential Pin Placement Guidelines” on page 8–38
Differential I/O buffer
Transmitter serializer
Receiver deserializer
8. High-Speed Differential I/O Interfaces
and DPA in Stratix IV Devices
®
IV FPGAs. All
Subscribe