DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 166

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

5–50
Table 5–16. Dynamic Phase-Shifting Control Signals (Part 1 of 2)
Stratix IV Device Handbook Volume 1
PHASECOUNTERSELECT
[3..0]
PHASEUPDOWN
PHASESTEP
Signal Name
1
Bypassing a PLL
Bypassing a PLL counter results in a multiply (m counter) or a divide (n and C0 to C9
counters) factor of one.
Table 5–15
Table 5–15. PLL Counter Settings
To bypass any of the PLL counters, set the bypass bit to 1. The values on the other bits
are ignored. To bypass the VCO post-scale counter (K), set the corresponding bit to 0.
Dynamic Phase-Shifting
The dynamic phase-shifting feature allows the output phases of individual PLL
outputs to be dynamically adjusted relative to each other and to the reference clock,
without having to send serial data through the scan chain of the corresponding PLL.
This feature simplifies the interface and allows you to quickly adjust the clock-to-out
(t
achieved by incrementing or decrementing the VCO phase-tap selection to a given C
counter or to the M counter. The phase is shifted by 1/8 of the VCO frequency at a
time. The output clocks are active during this phase-reconfiguration process.
Table 5–16
Note to
(1) Counter-bypass bit.
LSB
CO
X
X
Counter select. Four bits decoded to
select either the M or one of the C
counters for phase adjustment. One
address maps to select all C counters.
This signal is registered in the PLL on
the rising edge of SCANCLK.
Selects dynamic phase shift direction;
1 = UP; 0 = DOWN. Signal is registered
in the PLL on the rising edge of
SCANCLK.
Logic high enables dynamic phase
shifting.
) delays by changing the output clock phase-shift in real time. This adjustment is
Table
X
X
lists the settings for bypassing the counters in Stratix IV PLLs.
lists the control signals that are used for dynamic phase-shifting.
5–15:
Description
X
X
X
X
X
X
PLL Scan Chain Bits [0..8] Settings
X
X
X
X
Logic array or I/O pins
Logic array or I/O pin
Logic array or I/O pin
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
X
X
Source
1
0
MSB
(1)
(1)
PLL counter bypassed
PLL counter not bypassed because
bit 8 (MSB) is set to 0
PLL reconfiguration circuit
PLL reconfiguration circuit
PLL reconfiguration circuit
February 2011 Altera Corporation
Description
Destination
PLLs in Stratix IV Devices