DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 664
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 664 of 1154
- Download datasheet (32Mb)
1–220
Table 1–76. Stratix IV GX and GT ALTGX Megafunction Ports: Dynamic Reconfiguration (Part 2 of 2)
Table 1–77. Stratix IV GX and GT ALTGX Megafunction Ports: PCIe Interface (Part 1 of 4)
Stratix IV Device Handbook Volume 2: Transceivers
reconfig_togxb
reconfig_fromgxb
powerdn
tx_
forcedispcompliance
tx_forceelecidle
rateswitch
Port Name
Port Name
Table 1–77
Output
Output
Input/
Input
Output
Input/
Input
Input
Input
Input
PCIe Interface (Available only in PCIe functional Mode)
lists the ALTGX megafunction PCIe interface ports.
Clock Domain
Asynchronous
Asynchronous
Clock Domain
Asynchronous
Asynchronous
Asynchronous
Asynchronous
signal
signal
signal
signal
signal
signal
From the dynamic reconfiguration controller.
To the dynamic reconfiguration controller.
PCIe power state control.
■
■
Force 8B/10B encoder to encode with a negative
running disparity.
■
■
Force transmitter buffer to PCIe electrical idle
signal levels.
■
■
PCIe rateswitch control.
■
■
Functionally equivalent to the powerdown[1:0]
signal defined in the PCIe specification revision
2.0.
The width of this signal is 2 bits and is encoded
as follows:
■
■
■
■
Functionally equivalent to the txcompliance
signal defined in PCIe specification revision 2.0.
Must be asserted high only when transmitting
the first byte of the PCIe compliance pattern to
force the 8B/10B encode with a negative running
disparity as required by the PCIe protocol.
Functionally equivalent to the txelecidle
signal defined in the PCIe specification revision
2.0.
Available in the Basic mode.
1’b0—Gen1 (2.5 Gbps)
1’b1—Gen2 (5 Gbps)
2'b00: P0—Normal Operation
2'b01: P0s—Low Recovery Time Latency,
Low Power State
2'b10: P1—Longer Recovery Time Latency,
Lower Power State
2'b11: P2—Lowest Power State
Chapter 1: Transceiver Architecture in Stratix IV Devices
Description
Description
February 2011 Altera Corporation
Transceiver Port Lists
Scope
Channel
Channel
Channel
Scope
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