DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 174
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 174 of 1154
- Download datasheet (32Mb)
6–2
I/O Standards Support
Stratix IV Device Handbook Volume 1
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This chapter contains the following sections:
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Stratix IV devices support a wide range of industry I/O standards.
I/O standards Stratix IV devices support, as well as the typical applications. These
devices support V
Table 6–1. I/O Standards and Applications for Stratix IV Devices (Part 1 of 2)
3.3-V LVTTL/LVCMOS (1),
2.5-V LVCMOS
1.8-V LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
3.0-V PCI/PCI-X
SSTL-2 Class I and II
SSTL-18 Class I and II
SSTL-15 Class I and II
HSTL-18 Class I and II
HSTL-15 Class I and II
HSTL-12 Class I and II
Differential SSTL-2 Class I and II
Differential SSTL-18 Class I and II
Differential SSTL-15 Class I and II
Differential HSTL-18 Class I and II
Programmable pull-up resistor
Open-drain output
Serial, parallel, and dynamic on-chip termination (OCT)
Differential OCT
Programmable pre-emphasis
Programmable equalization
Programmable differential output voltage (V
“I/O Standards Support”
“I/O Banks” on page 6–5
“I/O Structure” on page 6–17
“On-Chip Termination Support and I/O Termination Schemes” on page 6–24
“OCT Calibration” on page 6–32
“Termination Schemes for I/O Standards” on page 6–38
“Design Considerations” on page 6–46
I/O Standard
CCIO
voltage levels of 3.0, 2.5, 1.8, 1.5, and 1.2 V.
(2)
General purpose
General purpose
General purpose
General purpose
General purpose
DDR SDRAM
DDR2 SDRAM
DDR3 SDRAM
QDRII/RLDRAM II
QDRII/QDRII+/RLDRAM II
General purpose
DDR SDRAM
DDR2 SDRAM
DDR3 SDRAM
Clock interfaces
PC and embedded system
OD
)
Chapter 6: I/O Features in Stratix IV Devices
Application
February 2011 Altera Corporation
Table 6–1
I/O Standards Support
lists the
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