DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 808

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

4–2
User Reset and Power-Down Signals
Table 4–1. Transceiver Channel Reset Signals
Stratix IV Device Handbook Volume 2: Transceivers
tx_digitalreset
rx_digitalreset
rx_analogreset
Note to
(1) Assert this signal until the clocks coming out of the transmitter PLL and receiver CDR are stabilized. Stable parallel clocks are essential for
proper operation of the transmitter and receiver phase-compensation FIFOs in the PCS.
Table
4–1:
Signal
1
(1)
(1)
Each transceiver channel in the Stratix IV device has individual reset signals to reset
its physical coding sublayer (PCS) and physical medium attachment (PMA) blocks.
Each CMU PLL in the transceiver block has a dedicated reset signal. The transceiver
block also has a power-down signal that affects all the channels and CMU PLLs in the
transceiver block.
All reset and power-down signals are asynchronous.
Table 4–1
lists the reset signals available for each transceiver channel.
■
■
■
■
■
■
Transmitter Only
Receiver and Transmitter
Receiver Only
Receiver and Transmitter
Receiver Only
Receiver and Transmitter
ALTGX MegaWizard Plug-In
Manager Configurations
Chapter 4: Reset Control and Power Down in Stratix IV Devices
Provides asynchronous reset to all digital logic in
the transmitter PCS, including the XAUI transmit
state machine.
The minimum pulse width for this signal is two
parallel clock cycles.
Resets all digital logic in the receiver PCS,
including:
■
■
■
■
■
The minimum pulse width for this signal is two
parallel clock cycles.
Resets the receiver CDR present in the receiver
channel.
The minimum pulse width is two parallel clock
cycles.
XAUI receiver state machines
GIGE receiver state machines
XAUI channel alignment state machine
BIST-PRBS verifier
BIST-incremental verifier
Description
User Reset and Power-Down Signals
February 2011 Altera Corporation