DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 107

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Mode Descriptions
February 2011 Altera Corporation
High-Precision Multiplier Adder Mode
Four-multiplier adder mode supports the rounding and saturation logic unit. You can
use the pipeline registers and output registers within the DSP block to pipeline the
multiplier-adder result, increasing the performance of the DSP block.
In a high-precision multiplier adder configuration, shown in
page
precision of 18 x 36 (one two-multiplier adder per half DSP block). This mode is useful
in filtering or FFT applications where a data path greater than 18 bits is required, yet
18 bits is sufficient for the coefficient precision. This can occur where the data has a
high dynamic range. If the coefficients are fixed, as in FFT and most filter applications,
the precision of 18 bits provide a dynamic range over 100 dB, if the largest coefficient
is normalized to the maximum 18-bit representation.
In these situations, the data path can be up to 36 bits, allowing sufficient capacity for
bit growth or gain changes in the signal source without loss of precision. This mode is
also extremely useful in single precision block floating point applications.
The high-precision multiplier adder is performed in two stages. The 18 × 36 multiply
is divided into two 18 × 18 multipliers. The multiplier with the LSB of the data source
is performed unsigned, while the multiplier with the MSB of the data source can be
signed or unsigned. The latter multiplier has its result left shifted by 18 bits prior to
the first adder stage, creating an effective 18 x 36 multiplier. The results of these two
adder blocks are then summed in the second stage adder block to produce the final
result:
Z[54..0] = P
where:
P
P
0
1
= A[17..0] × B[35..0]
= C[17..0] × D[35..0]
4–28, the DSP block can implement 2 two-multiplier adders, with multiplier
0
[53..0] + P
1
[53..0]
Stratix IV Device Handbook Volume 1
Figure 4–18 on
4–27