DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 506

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

1–62
Figure 1–51. Word Aligner Configured in Bit-Slip Mode
Stratix IV Device Handbook Volume 2: Transceivers
rx_patterndetect
rx_dataout[7:0]
rx_datain
rx_clkout
rx_bitslip
Basic single-width mode with 8-bit PMA-PCS interface width allows the word aligner
to be configured in bit-slip mode. The word aligner operation is controlled by the
input signal rx_bitslip in bit-slip mode. At every rising edge of the rx_bitslip
signal, the bit-slip circuitry slips one bit into the received data stream, effectively
shifting the word boundary by one bit. In bit-slip mode, the word aligner status signal
rx_patterndetect is driven high for one parallel clock cycle when the received data
after bit-slipping matches the 16-bit word alignment pattern programmed in the
ALTGX MegaWizard Plug-In Manager.
You can implement a bit-slip controller in the FPGA fabric that monitors either the
rx_dataout signal and/or the rx_patterndetect signal and controls the rx_bitslip
signal to achieve word alignment.
Figure 1–51
this example, consider that 8'b11110000 is received back-to-back and
16'b0000111100011110 is specified as the word alignment pattern. A rising edge on the
rx_bitslip signal at time n + 1 slips a single bit 0 at the MSB position, forcing the
rx_dataout to 8'b01111000. Another rising edge on the rx_bitslip signal at time n + 5
forces rx_dataout to 8'b00111100. Another rising edge on the rx_bitslip signal at
time n + 9 forces rx_dataout to 8'b00011110. Another rising edge on the rx_bitslip
signal at time n + 13 forces the rx_dataout to 8'b00001111. At this instance,
rx_dataout in cycles n + 12 and n + 13 is 8'b00011110 and 8'b00001111, respectively,
which matches the specified 16-bit alignment pattern 16'b0000111100011110. This
results in the assertion of the rx_patterndetect signal.
11110000
Bit-Slip Mode Word Aligner with 8-Bit PMA-PCS Interface Modes
n
shows an example of the word aligner configured in bit-slip mode. For
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 n + 10 n + 11 n + 12 n + 13 n + 14
01111000
11110000
00111100
Chapter 1: Transceiver Architecture in Stratix IV Devices
00011110
February 2011 Altera Corporation
Transceiver Block Architecture
00001111