DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 731

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 2: Transceiver Clocking in Stratix IV Devices
FPGA Fabric-Transceiver Interface Clocking
Figure 2–32. Sixteen Identical Channels Across Four Transceiver Blocks for Example 5
February 2011 Altera Corporation
Common Clock Driver Selection Rules
The common clock driver driving the tx_coreclk ports of all identical channels must
have 0 PPM frequency difference with respect to the transmitter phase compensation
FIFO read clocks of these channels. If there is any frequency difference between the
FIFO write clock (tx_coreclk) and the FIFO read clock, the FIFO overflows or
under-runs, resulting in corrupted data transfer between the FPGA fabric and the
transmitter.
Channel [15:12]
Channel [3:0]
Channel [11:8]
and Control
and Control
Channel [7:4]
and Control
and Control
TX Data
TX Data
TX Data
TX Data
Logic
Logic
Logic
Logic
FPGA
Fabric
tx_coreclk[15:12]
tx_coreclk[3:0]
tx_coreclk[11:8]
tx_coreclk[7:4]
Clock Driver
Common
tx_clkout[12]
tx_clkout[8]
tx_clkout[4]
tx_clkout[0]
Transceiver Block
Transceiver Block
Transceiver Block
Transceiver Block
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Stratix IV Device Handbook Volume 2: Transceivers
GXBR
GXBR3
GXBR
GXBR
2
0
1
2–59