DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 275

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
February 2011 Altera Corporation
I/O Configuration Block and DQS Configuration Block
The I/O configuration block and the DQS configuration block are shift registers that
you can use to dynamically change the settings of various device configuration bits.
The shift registers power-up low. Every I/O pin contains one I/O configuration
register, while every DQS pin contains one DQS configuration block in addition to the
I/O configuration register.
DQS configuration block circuitry.
Figure 7–36. I/O Configuration Block and DQS Configuration Block
Table 7–19
Table 7–19. I/O Configuration Block Bit Sequence
Table 7–20
Table 7–20. DQS Configuration Block Bit Sequence (Part 1 of 2)
11..14
15..18
19..22
27..29
30..33
7..10
7..10
0..3
4..6
0..3
4..6
Bit
Bit
23
24
25
26
lists the I/O configuration block bit sequence.
lists the DQS configuration block bit sequence.
update
datain
ena
clk
Figure 7–36
bit 0
bit 1
shows the I/O configuration block and the
padtoinputregisterdelaysetting[0..3]
dqsenablectrlphasesetting[0..3]
resyncinputphasesetting[0..3]
dqsoutputphasesetting[0..3]
dqsbusoutdelaysetting[0..3]
dqsenabledelaysetting[0..2]
dqsinputphasesetting[0..2]
dqoutputphasesetting[0..3]
enaoutputcycledelaysetting
bit 2
enainputcycledelaysetting
outputdelaysetting1[0..3]
outputdelaysetting2[0..2]
enaoctcycledelaysetting
octdelaysetting1[0..3]
dividerphasesetting
Bit Name
Bit Name
Stratix IV Device Handbook Volume 1
MSB
7–55