DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 504
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 504 of 1154
- Download datasheet (32Mb)
1–60
Figure 1–49. Word Aligner in All Supported Configurations
Stratix IV Device Handbook Volume 2: Transceivers
Basic Single-Width)
(OC-12, OC-48,
Alignment
Manual
8-Bit Wide
Single-Width)
Bit-Slip
(Basic
Figure 1–49
In single-width mode, the PMA-PCS interface is either 8 or 10 bits wide. In 8-bit wide
PMA-PCS interface modes, the word aligner receives 8-bit wide data from the
deserializer. In 10-bit wide PMA-PCS interface modes, the word aligner receives
10-bit wide data from the deserializer. Depending on the configured functional mode,
you can configure the word aligner in manual alignment mode, automatic
synchronization state machine mode, or bit-slip mode.
The following functional modes support the 8-bit PMA-PCS interface:
■
■
■
Table 1–26
8-bit PMA-PCS interface.
Table 1–26. Word Aligner Configurations with an 8-Bit PMA-PCS Interface
In manual alignment mode, the word aligner operation is controlled by the input
signal rx_enapatternalign. The word aligner operation is edge-sensitive to the
rx_enapatternalign signal. After de-assertion of rx_digitalreset, a rising edge on
the rx_enapatternalign signal triggers the word aligner to look for the word
alignment pattern in the received data stream. In SONET/SDH OC-12 and OC-48
modes, the word aligner looks for 16'hF628 (A1A2) or 32'hF6F62828 (A1A1A2A2),
SONET/SDH OC-12
SONET/SDH OC-48
Basic single-width
SONET/SDH OC-12
SONET/SDH OC-48
Basic single-width
Word Aligner in Single-Width Mode
Functional Mode
Single-Width)
Alignment
Single-Width
Word Aligner in Single-Width Mode with 8-Bit PMA-PCS Interface Modes
Manual Alignment Mode Word Aligner with 8-Bit PMA-PCS Interface Modes
Manual
(Basic
lists the word aligner configurations allowed in functional modes with an
shows the word aligner operation in all supported configurations.
Basic Single-Width,
Synchronization
Serial RapidIO)
State Machine
XAUI, GIGE,
Automatic
(PCIe
10-Bit Wide
(Basic Single-Width,
Bit-Slip
Allowed Word Configurations
SDI)
PMA-PCS Interface Width
Manual Alignment, Bit-Slip
Manual Alignment
Manual Alignment
Double-Width,
Alignment
Manual
OC-96)
(Basic
Chapter 1: Transceiver Architecture in Stratix IV Devices
16-Bit Wide
Double-Width)
Bit-Slip
(Basic
Double-Width
February 2011 Altera Corporation
Allowed Word Alignment
Double-Width)
Alignment
Transceiver Block Architecture
Manual
(Basic
Pattern Length
16 bits
16 bits
16 bits
20-Bit Wide
Double-Width)
Bit-Slip
(Basic
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