DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 313

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Source-Synchronous Timing Budget
February 2011 Altera Corporation
1
For LVDS receivers, the Quartus II software provides an RSKM report showing the
SW, TUI, and RSKM values for non-DPA mode. You can generate the RSKM report by
executing the report_RSKM command in the TimeQuest Timing Analyzer. You can
find the RSKM report in the Quartus II compilation report under the TimeQuest
Timing Analyzer section.
In order to obtain the RSKM value, you must assign an appropriate input delay to the
LVDS receiver through the TimeQuest Timing Analyzer constraints menu.
For assigning input delay, follow these steps:
1. The Quartus II TimeQuest Timing Analyzer GUI has many options for setting the
Figure 8–28. Selection of Constraint Menu in TimeQuest Timing Analyzer
constraints and analyzing the design.
the Constraints menu. For setting input delay, you must select the Set Input Delay
option.
Figure 8–28
shows various commands on
Stratix IV Device Handbook Volume 1
8–35