DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 85

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Simplified DSP Operation
Figure 4–3. Four-Multiplier Adder and Accumulation Capability
February 2011 Altera Corporation
Input
Data
144
Following the two-multiplier adder units are the pipeline registers, the second-stage
adders, and an output register stage. You can configure the second-stage adders to
provide the alternative functions per half block, as shown in
Equation
Equation 4–2. Four-Multiplier Adder Equation
Equation 4–3. Four-Multiplier Adder Equation (44-Bit Accumulation)
In these equations, n denotes sample time and P[36..0] denotes the result from the
two-multiplier adder units.
Equation 4–2
(four-multiplier adder).
operation but with a maximum 44-bit accumulation capability by feeding the output
of the unit back to itself, as shown in
Depending on the mode you select, you can bypass all register stages except
accumulation and loopback mode. In these two modes, one set of registers must be
enabled. If the register set is not enabled, an infinite loop occurs.
Half-DSP Block
4–3.
provides a sum of four 18 × 18-bit multiplication operations
Equation 4–3
W
Z[37..0] = P
n
[43..0] = W
Figure
provides a four 18 × 18-bit multiplication
0
n-1
[36..0] + P
[43..0] ± Z
4–3.
1
[36..0]
n
[37..0]
Stratix IV Device Handbook Volume 1
Equation 4–2
44
Result[]
and
4–5