DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 717

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 2: Transceiver Clocking in Stratix IV Devices
Transceiver Channel Datapath Clocking
Table 2–11. Receiver Datapath Clock Frequencies in x4 Bonded Functional Modes with Deskew FIFO
February 2011 Altera Corporation
PCIe ×4 (Gen 1)
PCIe ×4 (Gen 2)
XAUI
Functional Mode
The parallel recovered clock from the receiver PMA in each channel clocks the word
aligner in that channel. The parallel recovered clock from Channel 0 clocks the
deskew FIFO and the write port of the rate match FIFO in all four bonded channels.
The low-speed parallel clock from the CMU0 clock divider block in CMU0_Channel clocks
the read port of the rate match FIFO, the 8B/10B decoder, and the write port of the
byte deserializer (if enabled) in all four bonded channels. The low-speed parallel clock
or its divide-by-two version (if byte deserializer is enabled) clocks the write port of
the receiver phase compensation FIFO. It is also driven on the coreclkout port as the
FPGA fabric-Transceiver interface clock. You can use the coreclkout signal to latch
the receiver data and status signals in the FPGA fabric for all four bonded channels.
Table 2–11
with deskew FIFO.
Data Rate
(Gbps)
3.125
2.5
5
lists the receiver datapath clock frequencies in ×4 bonded functional modes
Serial Recovered
Clock Frequency
1.5625 MHz
1.25 GHz
2.5 GHz
Transmitter PCS Clock
Parallel Recovered
Clock and Parallel
Frequency (MHz)
312.5
250
500
Stratix IV Device Handbook Volume 2: Transceivers
Without Byte
Deserializer
Interface Clock Frequency
FPGA-Fabric Transceiver
(MHz)
250
N/A
N/A
Deserializer
With Byte
156.25
(MHz)
125
250
2–45