DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 438
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 438 of 1154
- Download datasheet (32Mb)
vi
Chapter 5. Dynamic Reconfiguration in Stratix IV Devices
Stratix IV Device Handbook Volume 2: Transceivers
User Reset and Power-Down Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
Transceiver Reset Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4
PMA Direct Drive Mode Reset Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–24
Dynamic Reconfiguration Reset Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–36
Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–38
Simulation Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–39
Reference Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–39
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–40
Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
Dynamic Reconfiguration Controller Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3
Quartus II MegaWizard Plug-In Manager Interfaces to Support Dynamic Reconfiguration . . . . . . . . 5–4
Dynamic Reconfiguration Modes Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12
Blocks Affected by the Reset and Power-Down Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
All Supported Functional Modes Except PCIe Functional Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6
PCIe Functional Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–22
Basic (PMA Direct) Drive ×N Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–25
Basic (PMA Direct) Drive x1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–31
Reset Sequence when Using Dynamic Reconfiguration with the ‘data rate division in TX’ Option . . .
4–36
Reset Sequence when Using Dynamic Reconfiguration with the ‘Channel and TX PLL select/reconfig’
Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–37
ALTGX MegaWizard Plug-In Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4
ALTGX_RECONFIG MegaWizard Plug-In Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
Interfacing ALTGX and ALTGX_RECONFIG Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
PMA Controls Reconfiguration Mode Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12
Transceiver Channel Reconfiguration Mode Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–19
Offset Cancellation Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–66
EyeQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–68
Bonded Channel Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6
Non-Bonded Channel Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–15
PCIe Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–22
PCIe Initialization/Compliance Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–23
PCIe Normal Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–23
Transmitter Only Channel with No PLL_L/R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–25
Transmitter Only Channel with a PLL_L/R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–26
Receiver and Transmitter Channel Set-Up—Receiver CDR in Automatic Lock Mode . . . . . . . 4–32
Receiver and Transmitter Channel Set-up—Receiver CDR in Manual Lock Mode . . . . . . . . . . 4–34
The reconfig_clk Clock Requirements for the ALTGX Instance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4
The reconfig_clk Clock Requirements for the ALTGX_RECONFIG Instance . . . . . . . . . . . . . . . . 5–5
Logical Channel Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
Total Number of Channels Option in the ALTGX_RECONFIG Instance . . . . . . . . . . . . . . . . . . . 5–10
Connecting the ALTGX and ALTGX_RECONFIG Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11
Dynamically Reconfiguring PMA Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13
Memory Initialization File (.mif) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–20
Channel and CMU PLL Reconfiguration Mode Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–24
Channel Reconfiguration with Transmitter PLL Select Mode Details . . . . . . . . . . . . . . . . . . . . . . 5–47
CMU PLL Reconfiguration Mode Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–53
Central Control Unit Reconfiguration Mode Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–56
Special Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–56
Data Rate Division in Transmitter Mode Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–62
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–66
ALTGX_RECONFIG Instance Signals Transition during Offset Cancellation . . . . . . . . . . . . . . . 5–67
February 2011 Altera Corporation
Contents
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