DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 816

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

4–10
Figure 4–5. Sample Reset Sequence for Four Receiver and Transmitter Channels—Receiver CDR in Manual Lock Mode
Notes to
(1) For t
(2) For t
(3) For t
Stratix IV Device Handbook Volume 2: Transceivers
Output Status Signals
CDR Control Signals
Figure
pll_powerdown
LTR_LTD_Manual
LTD_Manual
rx_locktorefclk[0]
rx_locktorefclk[3]
rx_locktodata[0]
rx_locktodata[3]
Reset Signals
rx_pll_locked[0]
pll _ powerdown
rx _analogreset
rx_pll_locked[3]
tx _digitalreset
rx _digitalreset
4–5:
duration, refer to the
pll _ locked
duration, refer to the
duration, refer to the
busy
Receiver and Transmitter Channel—Receiver CDR in Manual Lock Mode
This configuration contains both a transmitter and receiver channel. For XAUI
functional mode, with the receiver CDR in manual lock mode, use the reset sequence
shown in
1
t
pll_powerdown (1)
DC and Switching Characteristics for Stratix IV Devices
Figure
DC and Switching Characteristics for Stratix IV Devices
DC and Switching Characteristics for Stratix IV Devices
2
4–5.
4
3
Minimum of Two Parallel Clock Cycles
5
6
7
7
t
Chapter 4: Reset Control and Power Down in Stratix IV Devices
LTR_LTD_Manual (2)
t
LTD_Manual (3)
8
8
8
8
chapter.
chapter.
chapter.
9
February 2011 Altera Corporation
Transceiver Reset Sequences