DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 145

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
February 2011 Altera Corporation
Source-Synchronous Mode for LVDS Compensation
The goal of source-synchronous mode is to maintain the same data and clock timing
relationship seen at the pins of the internal serializer/deserializer (SERDES) capture
register, except that the clock is inverted (180° phase shift). Thus, source-synchronous
mode ideally compensates for the delay of the LVDS clock network plus any
difference in delay between these two paths:
■
■
Figure 5–23
Figure 5–23. Phase Relationship Between the Clock and Data in LVDS Mode
No-Compensation Mode
In no-compensation mode, the PLL does not compensate for any clock networks. This
mode provides better jitter performance because the clock feedback into the PFD
passes through less circuitry. Both the PLL internal- and external-clock outputs are
phase-shifted with respect to the PLL clock input.
waveform of the PLL clocks’ phase relationship in no-compensation mode.
Figure 5–24. Phase Relationship Between the PLL Clocks in No Compensation Mode
Note to
(1) The PLL clock outputs lag the PLL input clocks depending on routine delays.
Data pin-to-SERDES capture register
Clock input pin-to-SERDES capture register. In addition, the output counter must
provide the 180° phase shift
Figure
5–24:
shows an example waveform of the clock and data in LVDS mode.
External PLL Clock Outputs (1)
Register Clock Port (1)
Clock at register
Data at register
reference clock
PLL Clock at the
at input pin
PLL Reference
Data pin
Clock at the
PLL
Input Pin
Phase Aligned
Figure 5–24
Stratix IV Device Handbook Volume 1
shows an example
5–29