DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 367

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Passive Serial Configuration
Figure 10–14. PS Configuration Using a USB Blaster, EthernetBlaster, MasterBlaster, ByteBlaster II, or ByteBlasterMV
Cable
Notes to
(1) Connect the pull-up resistor to the same supply voltage (V
(2) You only need the pull-up resistors on DATA0 and DCLK if the download cable is the only configuration scheme used on your board. This ensures
(3) Pin 6 of the header is a V
April 2011 Altera Corporation
EthernetBlaster cable.
that DATA0 and DCLK are not left floating after configuration. For example, if you are also using a configuration device, you do not need the
pull-up resistors on DATA0 and DCLK.
this value, refer to the
this pin is a no connect.
Figure
10–14:
1
MasterBlaster Serial/USB Communications Cable User
The configuration cycle consists of three stages—reset, configuration, and
initialization. While nCONFIG or nSTATUS are low, the device is in reset. To initiate
configuration in this scheme, the download cable generates a low-to-high transition
on the nCONFIG pin.
To begin configuration, power the V
banks where the configuration pins reside) to the appropriate voltage levels.
When nCONFIG goes high, the device comes out of reset and releases the open-drain
nSTATUS pin, which is then pulled high by an external 10-kΩ pull-up resistor. After
nSTATUS is released, the device is ready to receive configuration data and the
configuration stage begins. The programming hardware or download cable then
places the configuration data one bit at a time on the device’s DATA0 pin. The
configuration data is clocked into the target device until CONF_DONE goes high. The
CONF_DONE pin must have an external 10-kΩ pull-up resistor for the device to initialize.
When using a download cable, setting the Auto-restart configuration after error
option does not affect the configuration cycle because you must manually restart
configuration in the Quartus II software when an error occurs. Additionally, the
Enable user-supplied start-up clock (CLKUSR) option has no affect on the device
initialization because this option is disabled in the .sof when programming the device
using the Quartus II programmer and download cable. Therefore, if you turn on the
CLKUSR option, you do not need to provide a clock on CLKUSR when you are
configuring the device with the Quartus II programmer and a download cable.
Figure 10–14
EthernetBlaster, MasterBlaster, ByteBlaster II, or ByteBlasterMV cable.
IO
V
reference voltage for the MasterBlaster output driver. V
CCPGM
(2)
(1)
10
V
kΩ
CCPGM
(2)
10
kΩ
(1)
V
CCPGM
shows PS configuration for Stratix IV devices using a USB Blaster,
10
(1)
kΩ
V CCPGM
GND
GND
CCPGM
MSEL2
MSEL1
MSEL0
nCE
DCLK
DATA0
nCONFIG
) as the USB Blaster, MasterBlaster (VIO pin), ByteBlaster II, ByteBlasterMV, or
Stratix IV Device
CONF_DONE
nSTATUS
nCEO
CC
Guide. In the USB-Blaster, ByteBlaster II, and ByteBlasterMV cable,
, V
N.C.
IO
CCIO
V
CCPGM
must match the device’s V
, V
(1) V
10
kΩ
CCPGM
CCPGM
Pin 1
10
(1)
kΩ
10-Pin Male Header
Download Cable
, and V
(PS Mode)
Shield
GND
V
V
CCPGM
IO
Stratix IV Device Handbook Volume 1
(3)
GND
CCPD
CCPGM
(1)
. For more information about
voltages (for the
10–33