DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 817
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 817 of 1154
- Download datasheet (32Mb)
Chapter 4: Reset Control and Power Down in Stratix IV Devices
Transceiver Reset Sequences
February 2011 Altera Corporation
As shown in
follow these reset steps:
1. After power up, assert pll_powerdown for a minimum period of t
2. Keep the tx_digitalreset, rx_analogreset, rx_digitalreset, and
3. After the transmitter PLL locks, as indicated by the pll_locked signal going high
4. Wait for the rx_pll_locked signal from each channel to go high. The
5. In a bonded channel group, when the rx_pll_locked signal of all the channels
6. After asserting the rx_locktodata signal, wait for at least t
time between markers 1 and 2).
rx_locktorefclk signals asserted and the rx_locktodata signal de-asserted
during this time period. After you de-assert the pll_powerdown signal, the
transmitter PLL starts locking to the transmitter input reference clock.
(marker 3), de-assert the tx_digitalreset signal (marker 4). For the receiver
operation, after de-assertion of the busy signal, wait for a minimum of two parallel
clock cycles to de-assert the rx_analogreset signal. After the rx_analogreset
signal is de-asserted, the receiver CDR of each channel starts locking to the
receiver input reference clock because rx_locktorefclk is asserted.
rx_pll_locked signal of each channel may go high at different times with respect
to each other (indicated by the slashed pattern at marker 7).
have gone high, from that point onwards, wait for at least t
de-assert rx_locktorefclk and assert rx_locktodata (marker 8). At this point, the
receiver CDR of all the channels enters into lock-to-data mode and starts locking to
the received data.
de-asserting rx_digitalreset (the time between markers 8 and 9).
Figure
4–5, for the receiver CDR in manual lock mode configuration,
Stratix IV Device Handbook Volume 2: Transceivers
LTD_Manual
LTR_LTD_Manual
pll_powerdown
before
, then
(the
4–11
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