DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 936

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

5–90
Stratix IV Device Handbook Volume 2: Transceivers
PMA Controls Reconfiguration Duration When Using Method 1
The logical_channel_address port is used in Method 1. The write transaction and
read transaction duration is as follows:
For writing values to the following PMA controls, the busy signal is asserted for 260
reconfig_clk clock cycles for each of these controls:
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■
■
■
For writing values to the following PMA controls, the busy signal is asserted for 520
reconfig_clk clock cycles for each of these controls:
■
■
For reading the existing values of the following PMA controls, the busy signal is
asserted for 130 reconfig_clk clock cycles for each of these controls. The data_valid
signal is then asserted after the busy signal goes low.
■
■
■
■
For reading the existing values of the following PMA controls, the busy signal is
asserted for 260 reconfig_clk clock cycles for each of these controls. The data_valid
signal is then asserted after the busy signal goes low.
■
■
PMA Controls Reconfiguration Duration When Using Method 2 or Method 3
The logical_channel_address port is not used in Method 2 and Method 3. The write
transaction duration and read transaction duration are as follows:
For writing values to the following PMA controls, the busy signal is asserted for 260
reconfig_clk clock cycles per channel for each of these controls:
■
■
■
■
tx_preemp_1t (pre-emphasis control first post-tap)
tx_vodctrl (voltage output differential)
rx_eqctrl (equalizer control)
rx_eqdcgain (equalizer DC gain)
tx_preemp_0t (pre-emphasis control pre-tap)
tx_preemp_2t (pre-emphasis control second post-tap)
tx_preemp_1t_out (pre-emphasis control first post-tap)
tx_vodctrl_out (voltage output differential)
rx_eqctrl_out (equalizer control)
rx_eqdcgain_out (equalizer DC gain)
tx_preemp_0t_out (pre-emphasis control pre-tap)
tx_preemp_2t_out (pre-emphasis control second post-tap)
tx_preemp_1t (pre-emphasis control first post-tap)
tx_vodctrl (voltage output differential)
rx_eqctrl (equalizer control)
rx_eqdcgain (equalizer DC gain)
Write Transaction Duration
Read Transaction Duration
Write Transaction Duration
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
February 2011 Altera Corporation
Dynamic Reconfiguration Duration