DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 556

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

1–112
Stratix IV Device Handbook Volume 2: Transceivers
1
1
Table 1–43
in Basic single-width and double-width modes.
Table 1–43. PCS-PMA Interface Widths and Data Rates Supported in Basic Single-Width and
Double-Width Modes for Stratix IV GT Devices
Low Latency PCS Datapath
The ALTGX MegaWizard Plug-In Manager provides an Enable low latency PCS
mode option when configured in Basic single-width or Basic double-width mode. If
you select this option, the following transmitter and receiver channel PCS blocks are
bypassed to yield a low latency PCS datapath:
■
■
■
■
■
In low latency PCS modes, the transmitter and receiver phase compensation FIFOs are
always enabled. Depending on the targeted data rate, you can optionally bypass the
byte serializer and deserializer blocks. For more information, refer to
Width Mode Configurations” on page 1–113
Configurations” on page
The PCS latency in Basic single-width and Basic double-width modes with and
without the low latency PCS mode option is pending characterization.
Basic double-width mode configurations at data rates of > 6.5 Gbps are only allowed
in low-latency PCS bypass mode.
Basic single-width mode
Basic double-width mode
Note to
(1) The data rate range supported in Basic single-width and double-width modes varies depending on whether or not
8B/10B encoder and decoder
Word aligner
Deskew FIFO
Rate match (clock rate compensation) FIFO
Byte ordering
Basic Functional Mode
you use the byte serializer/deserializer. For more information, refer
on page 1–113
Table
lists the Stratix IV GT PCS-PMA interface widths and data rates supported
1–43:
and
“Basic Double-Width Mode Configurations” on page
1–117.
Supported Data Rate Range
600 Mbps to 3.75 Gbps
1.0 to 11.3 Gbps
(Note 1)
Chapter 1: Transceiver Architecture in Stratix IV Devices
and
“Basic Double-Width Mode
to“Basic Single-Width Mode Configurations”
1–117.
PMA-PCS Interface Width
February 2011 Altera Corporation
Transceiver Block Architecture
16-bit, 20-bit
8-bit, 10-bit
“Basic Single-