DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 1090
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
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- Download datasheet (32Mb)
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Electrical Characteristics
Table 1–11. OCT Without Calibration Resistance Tolerance Specifications for Stratix IV Devices
April 2011 Altera Corporation
25-Ω R
3.0 and 2.5
25-Ω R
1.8 and 1.5
25-Ω R
1.2
50-Ω R
3.0 and 2.5
50-Ω R
1.8 and 1.5
50-Ω R
1.2
100-Ω R
2.5
Symbol
S
S
S
S
S
S
D
The calibration accuracy for calibrated series and parallel OCTs are applicable at the
moment of calibration. When process, voltage, and temperature (PVT) conditions
change after calibration, the tolerance may change.
without calibration resistance tolerance to PVT changes.
OCT calibration is automatically performed at power-up for OCT-enabled I/Os.
Table 1–12
calibration. Use
and
Equation 1–1. OCT Variation Without Re-Calibration
Notes to
(1) The R
(2) R
(3) ΔT is the variation of temperature with respect to the temperature at power-up.
(4) ΔV is the variation of voltage with respect to the V
(5) dR/dT is the percentage change of R
(6) dR/dV is the percentage change of R
Internal series termination
without calibration (25-Ω
setting)
Internal series termination
without calibration (25-Ω
setting)
Internal series termination
without calibration (25-Ω
setting)
Internal series termination
without calibration (50-Ω
setting)
Internal series termination
without calibration (50-Ω
setting)
Internal series termination
without calibration (50-Ω
setting)
Internal differential
termination (100-Ω setting)
and V
Equation 1–1
SCAL
Equation
CCIO
OCT
is the OCT resistance value at power-up.
Description
.
value calculated from
lists OCT variation with temperature and voltage after power-up
1–1:
Table 1–12
to determine the OCT variation without re-calibration.
R
OCT
Equation 1–1
to determine the OCT variation after power-up calibration
=
V
V
V
V
CCIO
CCIO
CCIO
CCIO
SCAL
SCAL
R
SCAL
V
V
V
Conditions
with temperature.
with voltage.
= 3.0 and 2.5 V
= 1.8 and 1.5 V
CCIO
= 3.0 and 2.5 V
= 1.8 and 1.5 V
CCIO
CCIO
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
shows the range of OCT resistance with the variation of temperature
⎛
⎝
= 1.2 V
= 1.2 V
= 2.5 V
1
+
CCIO
〈
dR
------ -
at power-up.
dT
×
(Note
ΔT
〉
±
± 30
± 30
± 35
± 30
± 30
± 35
± 25
Table 1–11
C2
〈
1), (2), (3), (4), (5),
dR
------ -
dV
Resistance Tolerance
×
ΔV
C3,I3
〉
lists the Stratix IV OCT
± 40
± 40
± 50
± 40
± 40
± 50
± 25
⎞
⎠
(6)
C4,I4
± 40
± 40
± 50
± 40
± 40
± 50
± 25
Unit
%
%
%
%
%
%
%
1–8
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