DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 693

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 2: Transceiver Clocking in Stratix IV Devices
Transceiver Channel Datapath Clocking
February 2011 Altera Corporation
Transmitter Channel-to-Channel Skew Optimization for Modes Other than
Basic (PMA Direct) Mode
High-speed serial clock and low-speed parallel clock skew between channels and
unequal latency in the transmitter phase compensation FIFO contribute to transmitter
channel-to-channel skew. Transmitter datapath clocking is set up to provide low
channel-to-channel skew when compared with non-bonded channel configurations.
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In bonded channel configurations—the high-speed serial clock and low-speed
parallel clock for all bonded channels are generated by the CMU0 clock divider or
the ATX clock divider block, resulting in lower channel-to-channel clock skew.
The transmitter phase compensation FIFO in all bonded channels (except in Basic
[PMA Direct] ×N mode) share common pointers and control logic generated in the
central control unit (CCU), resulting in equal latency in the transmitter phase
compensation FIFO of all bonded channels. The lower transceiver clock skew and
equal latency in the transmitter phase compensation FIFOs in all channels
provides lower channel-to-channel skew in bonded channel configurations.
In non-bonded channel configurations—the high-speed serial clock and low-speed
parallel clock in each channel are generated independently by its local clock
divider. This results in higher channel-to-channel clock skew.
The transmitter phase compensation FIFO in each non-bonded channel (except in
Basic [PMA Direct] mode) has its own pointers and control logic that can result in
unequal latency in the transmitter phase compensation FIFO of each channel. The
higher transceiver clock skew and unequal latency in the transmitter phase
compensation FIFO in each channel can result in higher channel-to-channel skew.
Stratix IV Device Handbook Volume 2: Transceivers
2–21