DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 416

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

11–10
Stratix IV Device Handbook Volume 1
Software Support
Table 11–7
maximum clock frequencies for Stratix IV devices. The minimum CRC calculation
time is calculated by using the maximum error detection frequency with a divisor
factor of one, and the maximum CRC calculation time is calculated by using the
minimum error detection frequency with a divisor factor of eight.
Table 11–7. CRC Calculation Time
The Quartus II software version 8.0 and onwards supports the error detection CRC
feature for Stratix IV devices. Enabling this feature generates the CRC_ERROR output to
the optional dual purpose CRC_ERROR pin.
The error detection CRC feature is controlled by the Device and Pin Options dialog
box in the Quartus II software.
To enable the error detection feature using CRC, follow these steps:
1. Open the Quartus II software and load a project using a Stratix IV device.
2. On the Assignments menu, click Settings. The Settings dialog box is shown.
3. In the Category list, select Device. The Device page is shown.
4. Click Device and Pin Options. The Device and Pin Options dialog box is shown
Note to
(1) These timing numbers are preliminary.
(refer to
Table
lists the estimated time for each CRC calculation with minimum and
11–7:
Figure
EP4SGX110
EP4SGX180
EP4SGX230
EP4SGX290
EP4SGX360
EP4SGX530
EP4S100G2
EP4S100G3
EP4S100G4
EP4S100G5
EP4SGX70
EP4S40G2
EP4S40G5
EP4SE230
EP4SE360
EP4SE530
EP4SE820
Device
11–2).
(Note 1)
Minimum Time (ms)
111
111
225
225
296
296
398
225
296
398
577
225
398
225
398
398
398
Chapter 11: SEU Mitigation in Stratix IV Devices
February 2011 Altera Corporation
Maximum Time (s)
Error Detection Timing
110.38
110.38
160.00
110.38
110.38
110.38
110.38
30.90
30.90
62.44
62.44
82.05
82.05
62.44
82.05
62.44
62.44